/**
*   @ file    S32K14x_Resource.m
*   @ version 1.0.1
*
*   @ brief   AUTOSAR Port - Resource for this platform
*   @ details Resource for this platform
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.2 MCAL
*   Platform             : ARM
*   Peripheral           : PORT_CI
*   Dependencies         : none
*
*   Autosar Version      : 4.2.2
*   Autosar Revision     : ASR_REL_4_2_REV_0002
*   Autosar Conf.Variant :
*   SW Version           : 1.0.1
*   Build Version        : S32K14x_MCAL_1_0_1_RTM_HF3_ASR_REL_4_2_REV_0002_20180821
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017-2018 NXP
*   All Rights Reserved.
==================================================================================================*/
[!IF "not(var:defined('PORT_RESOURCE_M'))"!]
[!VAR "PORT_RESOURCE_M"="'true'"!]
[!VAR "PinMap"!]
ADC0_SE0_CMP0_IN0_PORT0;0:[!//
FTM2_CH1_PORT0;2:[!//
FTM2_CH1_PORT0;2:[!//
FTM2_CH1_PORT0;2:[!//
FTM2_CH1_PORT0;2:[!//
LPI2C0_SCLS_PORT0;3:[!//
FXIO_D2_PORT0;4:[!//
FTM2_QD_PHA_PORT0;5:[!//
FTM2_QD_PHA_PORT0;5:[!//
FTM2_QD_PHA_PORT0;5:[!//
FTM2_QD_PHA_PORT0;5:[!//
LPUART0_CTS_PORT0;6:[!//
TRGMUX_OUT3_PORT0;7:[!//
ADC0_SE1_CMP0_IN1_PORT1;0:[!//
FTM1_CH1_PORT1;2:[!//
LPI2C0_SDAS_PORT1;3:[!//
FXIO_D3_PORT1;4:[!//
FTM1_QD_PHA_PORT1;5:[!//
LPUART0_RTS_PORT1;6:[!//
TRGMUX_OUT0_PORT1;7:[!//
ADC1_SE0_PORT2;0:[!//
ADC1_SE0_PORT2;0:[!//
ADC1_SE0_PORT2;0:[!//
ADC1_SE0_PORT2;0:[!//
FTM3_CH0_PORT2;2:[!//
FTM3_CH0_PORT2;2:[!//
FTM3_CH0_PORT2;2:[!//
FTM3_CH0_PORT2;2:[!//
LPI2C0_SDA_PORT2;3:[!//
EWM_OUT_b_PORT2;4:[!//
EWM_OUT_b_PORT2;4:[!//
EWM_OUT_b_PORT2;4:[!//
EWM_OUT_b_PORT2;4:[!//
FXIO_D4_PORT2;5:[!//
LPUART0_RX_PORT2;6:[!//
ADC1_SE1_PORT3;0:[!//
ADC1_SE1_PORT3;0:[!//
ADC1_SE1_PORT3;0:[!//
ADC1_SE1_PORT3;0:[!//
FTM3_CH1_PORT3;2:[!//
FTM3_CH1_PORT3;2:[!//
FTM3_CH1_PORT3;2:[!//
FTM3_CH1_PORT3;2:[!//
LPI2C0_SCL_PORT3;3:[!//
EWM_IN_PORT3;4:[!//
EWM_IN_PORT3;4:[!//
EWM_IN_PORT3;4:[!//
EWM_IN_PORT3;4:[!//
FXIO_D5_PORT3;5:[!//
LPUART0_TX_PORT3;6:[!//
CMP0_OUT_PORT4;4:[!//
EWM_OUT_b_PORT4;5:[!//
EWM_OUT_b_PORT4;5:[!//
EWM_OUT_b_PORT4;5:[!//
EWM_OUT_b_PORT4;5:[!//
JTAG_TMS_SWD_DIO_PORT4;7:[!//
TCLK1_PORT5;3:[!//
RESET_b_PORT5;7:[!//
ADC0_SE2_PORT6;0:[!//
FTM0_FLT1_PORT6;2:[!//
LPSPI1_PCS1_PORT6;3:[!//
FTM5_CH5_PORT6;4:[!//
FTM5_CH5_PORT6;4:[!//
LPUART1_CTS_PORT6;6:[!//
ADC0_SE3_PORT7;0:[!//
FTM0_FLT2_PORT7;2:[!//
FTM5_CH3_PORT7;3:[!//
FTM5_CH3_PORT7;3:[!//
RTC_CLKIN_PORT7;4:[!//
LPUART1_RTS_PORT7;6:[!//
LPUART2_RX_PORT8;2:[!//
LPUART2_RX_PORT8;2:[!//
LPUART2_RX_PORT8;2:[!//
LPSPI2_SOUT_PORT8;3:[!//
LPSPI2_SOUT_PORT8;3:[!//
LPSPI2_SOUT_PORT8;3:[!//
FXIO_D6_PORT8;4:[!//
FXIO_D6_PORT8;4:[!//
FXIO_D6_PORT8;4:[!//
FXIO_D6_PORT8;4:[!//
FTM3_FLT3_PORT8;5:[!//
FTM3_FLT3_PORT8;5:[!//
FTM3_FLT3_PORT8;5:[!//
FTM3_FLT3_PORT8;5:[!//
FTM4_FLT1_PORT8;6:[!//
FTM4_FLT1_PORT8;6:[!//
LPUART2_TX_PORT9;2:[!//
LPUART2_TX_PORT9;2:[!//
LPUART2_TX_PORT9;2:[!//
LPSPI2_PCS0_PORT9;3:[!//
LPSPI2_PCS0_PORT9;3:[!//
LPSPI2_PCS0_PORT9;3:[!//
FXIO_D7_PORT9;4:[!//
FXIO_D7_PORT9;4:[!//
FXIO_D7_PORT9;4:[!//
FXIO_D7_PORT9;4:[!//
FTM3_FLT2_PORT9;5:[!//
FTM3_FLT2_PORT9;5:[!//
FTM3_FLT2_PORT9;5:[!//
FTM3_FLT2_PORT9;5:[!//
FTM1_FLT3_PORT9;6:[!//
FTM1_FLT3_PORT9;6:[!//
FTM1_FLT3_PORT9;6:[!//
FTM1_FLT3_PORT9;6:[!//
FTM4_FLT0_PORT9;7:[!//
FTM4_FLT0_PORT9;7:[!//
FTM1_CH4_PORT10;2:[!//
FXIO_D0_PORT10;4:[!//
JTAG_TDO_PORT10;7:[!//
FTM1_CH5_PORT11;2:[!//
FXIO_D1_PORT11;4:[!//
CMP0_RRT_PORT11;5:[!//
SAI0_SYNC_PORT11;6:[!//
FTM1_CH6_PORT12;2:[!//
CAN1_RX_PORT12;3:[!//
CAN1_RX_PORT12;3:[!//
CAN1_RX_PORT12;3:[!//
CAN1_RX_PORT12;3:[!//
LPI2C1_SDAS_PORT12;4:[!//
FTM2_QD_PHB_PORT12;6:[!//
FTM2_QD_PHB_PORT12;6:[!//
FTM2_QD_PHB_PORT12;6:[!//
FTM2_QD_PHB_PORT12;6:[!//
SAI0_BCLK_PORT12;7:[!//
FTM1_CH7_PORT13;2:[!//
CAN1_TX_PORT13;3:[!//
CAN1_TX_PORT13;3:[!//
CAN1_TX_PORT13;3:[!//
CAN1_TX_PORT13;3:[!//
LPI2C1_SCLS_PORT13;4:[!//
FTM2_QD_PHA_PORT13;6:[!//
FTM2_QD_PHA_PORT13;6:[!//
FTM2_QD_PHA_PORT13;6:[!//
FTM2_QD_PHA_PORT13;6:[!//
SAI0_D0_PORT13;7:[!//
FTM0_FLT0_PORT14;2:[!//
FTM0_FLT0_PORT14;2:[!//
FTM0_FLT0_PORT14;2:[!//
FTM0_FLT0_PORT14;2:[!//
FTM3_FLT1_PORT14;3:[!//
FTM3_FLT1_PORT14;3:[!//
FTM3_FLT1_PORT14;3:[!//
FTM3_FLT1_PORT14;3:[!//
EWM_IN_PORT14;4:[!//
EWM_IN_PORT14;4:[!//
EWM_IN_PORT14;4:[!//
EWM_IN_PORT14;4:[!//
FTM1_FLT0_PORT14;6:[!//
FTM1_FLT0_PORT14;6:[!//
FTM1_FLT0_PORT14;6:[!//
FTM1_FLT0_PORT14;6:[!//
SAI0_D3_PORT14;7:[!//
ADC1_SE12_PORT15;0:[!//
ADC1_SE12_PORT15;0:[!//
ADC1_SE12_PORT15;0:[!//
ADC1_SE12_PORT15;0:[!//
FTM1_CH2_PORT15;2:[!//
FTM1_CH2_PORT15;2:[!//
FTM1_CH2_PORT15;2:[!//
FTM1_CH2_PORT15;2:[!//
LPSPI0_PCS3_PORT15;3:[!//
LPSPI0_PCS3_PORT15;3:[!//
LPSPI0_PCS3_PORT15;3:[!//
LPSPI0_PCS3_PORT15;3:[!//
LPSPI2_PCS3_PORT15;4:[!//
LPSPI2_PCS3_PORT15;4:[!//
LPSPI2_PCS3_PORT15;4:[!//
FTM7_FLT0_PORT15;5:[!//
ADC1_SE13_PORT16;0:[!//
ADC1_SE13_PORT16;0:[!//
ADC1_SE13_PORT16;0:[!//
ADC1_SE13_PORT16;0:[!//
FTM1_CH3_PORT16;2:[!//
FTM1_CH3_PORT16;2:[!//
FTM1_CH3_PORT16;2:[!//
FTM1_CH3_PORT16;2:[!//
LPSPI1_PCS2_PORT16;3:[!//
LPSPI1_PCS2_PORT16;3:[!//
LPSPI1_PCS2_PORT16;3:[!//
LPSPI1_PCS2_PORT16;3:[!//
FTM0_CH6_PORT17;2:[!//
FTM0_CH6_PORT17;2:[!//
FTM0_CH6_PORT17;2:[!//
FTM0_CH6_PORT17;2:[!//
FTM3_FLT0_PORT17;3:[!//
FTM3_FLT0_PORT17;3:[!//
FTM3_FLT0_PORT17;3:[!//
FTM3_FLT0_PORT17;3:[!//
EWM_OUT_b_PORT17;4:[!//
EWM_OUT_b_PORT17;4:[!//
EWM_OUT_b_PORT17;4:[!//
EWM_OUT_b_PORT17;4:[!//
FTM5_FLT0_PORT17;5:[!//
FTM5_FLT0_PORT17;5:[!//
FTM4_CH0_PORT18;2:[!//
LPUART1_TX_PORT18;3:[!//
LPSPI1_SOUT_PORT18;4:[!//
FTM6_CH0_PORT18;5:[!//
FTM4_CH1_PORT19;2:[!//
LPUART1_RX_PORT19;3:[!//
LPSPI1_SCK_PORT19;4:[!//
FTM4_CH2_PORT20;2:[!//
LPSPI1_SIN_PORT20;4:[!//
FTM4_CH3_PORT21;2:[!//
FXIO_D0_PORT21;3:[!//
LPSPI1_PCS0_PORT21;4:[!//
FTM4_CH4_PORT22;2:[!//
FXIO_D1_PORT22;3:[!//
LPSPI1_PCS1_PORT22;4:[!//
FTM4_CH6_PORT23;2:[!//
FXIO_D2_PORT23;3:[!//
FTM4_CH7_PORT24;2:[!//
FXIO_D3_PORT24;3:[!//
FTM5_CH0_PORT25;2:[!//
FTM5_CH0_PORT25;2:[!//
FTM5_CH1_PORT26;2:[!//
FTM5_CH1_PORT26;2:[!//
LPSPI1_PCS0_PORT26;3:[!//
LPSPI1_PCS0_PORT26;3:[!//
LPSPI0_PCS0_PORT26;4:[!//
LPSPI0_PCS0_PORT26;4:[!//
FTM5_CH2_PORT27;2:[!//
FTM5_CH2_PORT27;2:[!//
LPSPI1_SOUT_PORT27;3:[!//
LPSPI1_SOUT_PORT27;3:[!//
LPUART0_TX_PORT27;4:[!//
LPUART0_TX_PORT27;4:[!//
CAN0_TX_PORT27;5:[!//
CAN0_TX_PORT27;5:[!//
FTM5_CH3_PORT28;2:[!//
FTM5_CH3_PORT28;2:[!//
LPSPI1_SCK_PORT28;3:[!//
LPSPI1_SCK_PORT28;3:[!//
LPUART0_RX_PORT28;4:[!//
LPUART0_RX_PORT28;4:[!//
CAN0_RX_PORT28;5:[!//
CAN0_RX_PORT28;5:[!//
FTM5_CH4_PORT29;2:[!//
FTM5_CH4_PORT29;2:[!//
LPUART2_TX_PORT29;4:[!//
LPUART2_TX_PORT29;4:[!//
LPSPI1_SIN_PORT29;5:[!//
LPSPI1_SIN_PORT29;5:[!//
FTM5_CH5_PORT30;2:[!//
FTM5_CH5_PORT30;2:[!//
LPUART2_RX_PORT30;3:[!//
LPUART2_RX_PORT30;3:[!//
LPSPI0_SOUT_PORT30;4:[!//
LPSPI0_SOUT_PORT30;4:[!//
FTM5_CH6_PORT31;2:[!//
FTM5_CH6_PORT31;2:[!//
LPSPI0_PCS1_PORT31;4:[!//
LPSPI0_PCS1_PORT31;4:[!//
ADC0_SE4_ADC1_SE14_PORT32;0:[!//
LPUART0_RX_PORT32;2:[!//
LPSPI0_PCS0_PORT32;3:[!//
LPTMR0_ALT3_PORT32;4:[!//
CAN0_RX_PORT32;5:[!//
FTM4_CH6_PORT32;6:[!//
FTM4_CH6_PORT32;6:[!//
ADC0_SE5_ADC1_SE15_PORT33;0:[!//
LPUART0_TX_PORT33;2:[!//
LPSPI0_SOUT_PORT33;3:[!//
TCLK0_PORT33;4:[!//
CAN0_TX_PORT33;5:[!//
FTM4_CH5_PORT33;6:[!//
FTM4_CH5_PORT33;6:[!//
ADC0_SE6_PORT34;0:[!//
FTM1_CH0_PORT34;2:[!//
LPSPI0_SCK_PORT34;3:[!//
FTM1_QD_PHB_PORT34;4:[!//
TRGMUX_IN3_PORT34;6:[!//
ADC0_SE7_PORT35;0:[!//
FTM1_CH1_PORT35;2:[!//
LPSPI0_SIN_PORT35;3:[!//
FTM1_QD_PHA_PORT35;4:[!//
TRGMUX_IN2_PORT35;6:[!//
FTM0_CH4_PORT36;2:[!//
LPSPI0_SOUT_PORT36;3:[!//
MII_RMII_MDIO_PORT36;5:[!//
TRGMUX_IN1_PORT36;6:[!//
QSPI_B_IO0_PORT36;7:[!//
FTM0_CH5_PORT37;2:[!//
LPSPI0_PCS1_PORT37;3:[!//
LPSPI0_PCS0_PORT37;4:[!//
CLKOUT_PORT37;5:[!//
TRGMUX_IN0_PORT37;6:[!//
MII_RMII_MDC_PORT37;7:[!//
XTAL_PORT38;0:[!//
LPI2C0_SDA_PORT38;2:[!//
EXTAL_PORT39;0:[!//
LPI2C0_SCL_PORT39;2:[!//
FTM3_CH0_PORT40;2:[!//
FTM3_CH0_PORT40;2:[!//
FTM3_CH0_PORT40;2:[!//
FTM3_CH0_PORT40;2:[!//
SAI1_BCLK_PORT40;4:[!//
FTM3_CH1_PORT41;2:[!//
FTM3_CH1_PORT41;2:[!//
FTM3_CH1_PORT41;2:[!//
FTM3_CH1_PORT41;2:[!//
LPI2C0_SCLS_PORT41;3:[!//
LPI2C0_SCLS_PORT41;3:[!//
LPI2C0_SCLS_PORT41;3:[!//
LPI2C0_SCLS_PORT41;3:[!//
SAI1_D0_PORT41;4:[!//
FTM3_CH2_PORT42;2:[!//
FTM3_CH2_PORT42;2:[!//
FTM3_CH2_PORT42;2:[!//
FTM3_CH2_PORT42;2:[!//
LPI2C0_SDAS_PORT42;3:[!//
LPI2C0_SDAS_PORT42;3:[!//
LPI2C0_SDAS_PORT42;3:[!//
LPI2C0_SDAS_PORT42;3:[!//
SAI1_MCLK_PORT42;4:[!//
FTM3_CH3_PORT43;2:[!//
FTM3_CH3_PORT43;2:[!//
FTM3_CH3_PORT43;2:[!//
FTM3_CH3_PORT43;2:[!//
LPI2C0_HREQ_PORT43;3:[!//
LPI2C0_HREQ_PORT43;3:[!//
LPI2C0_HREQ_PORT43;3:[!//
LPI2C0_HREQ_PORT43;3:[!//
ADC1_SE7_PORT44;0:[!//
ADC1_SE7_PORT44;0:[!//
ADC1_SE7_PORT44;0:[!//
ADC1_SE7_PORT44;0:[!//
FTM0_CH0_PORT44;2:[!//
FTM3_FLT2_PORT44;3:[!//
FTM3_FLT2_PORT44;3:[!//
FTM3_FLT2_PORT44;3:[!//
FTM3_FLT2_PORT44;3:[!//
CAN2_RX_PORT44;4:[!//
CAN2_RX_PORT44;4:[!//
CAN2_RX_PORT44;4:[!//
FTM6_FLT1_PORT44;5:[!//
ADC1_SE8_ADC0_SE8_PORT45;0:[!//
FTM0_CH1_PORT45;2:[!//
FTM3_FLT1_PORT45;3:[!//
FTM3_FLT1_PORT45;3:[!//
FTM3_FLT1_PORT45;3:[!//
FTM3_FLT1_PORT45;3:[!//
CAN2_TX_PORT45;4:[!//
CAN2_TX_PORT45;4:[!//
CAN2_TX_PORT45;4:[!//
FTM6_FLT0_PORT45;5:[!//
ADC1_SE9_ADC0_SE9_PORT46;0:[!//
ADC1_SE9_ADC0_SE9_PORT46;0:[!//
ADC1_SE9_ADC0_SE9_PORT46;0:[!//
ADC1_SE9_ADC0_SE9_PORT46;0:[!//
FTM0_CH2_PORT46;2:[!//
FTM0_CH2_PORT46;2:[!//
FTM0_CH2_PORT46;2:[!//
FTM0_CH2_PORT46;2:[!//
LPSPI1_SCK_PORT46;3:[!//
LPSPI1_SCK_PORT46;3:[!//
LPSPI1_SCK_PORT46;3:[!//
LPSPI1_SCK_PORT46;3:[!//
ADC1_SE14_PORT47;0:[!//
ADC1_SE14_PORT47;0:[!//
ADC1_SE14_PORT47;0:[!//
ADC1_SE14_PORT47;0:[!//
FTM0_CH3_PORT47;2:[!//
FTM0_CH3_PORT47;2:[!//
FTM0_CH3_PORT47;2:[!//
FTM0_CH3_PORT47;2:[!//
LPSPI1_SIN_PORT47;3:[!//
LPSPI1_SIN_PORT47;3:[!//
LPSPI1_SIN_PORT47;3:[!//
LPSPI1_SIN_PORT47;3:[!//
ADC1_SE15_PORT48;0:[!//
ADC1_SE15_PORT48;0:[!//
ADC1_SE15_PORT48;0:[!//
ADC1_SE15_PORT48;0:[!//
FTM0_CH4_PORT48;2:[!//
FTM0_CH4_PORT48;2:[!//
FTM0_CH4_PORT48;2:[!//
FTM0_CH4_PORT48;2:[!//
LPSPI1_SOUT_PORT48;3:[!//
LPSPI1_SOUT_PORT48;3:[!//
LPSPI1_SOUT_PORT48;3:[!//
LPSPI1_SOUT_PORT48;3:[!//
FTM0_CH5_PORT49;2:[!//
FTM0_CH5_PORT49;2:[!//
FTM0_CH5_PORT49;2:[!//
FTM0_CH5_PORT49;2:[!//
LPSPI1_PCS3_PORT49;3:[!//
LPSPI1_PCS3_PORT49;3:[!//
LPSPI1_PCS3_PORT49;3:[!//
LPSPI1_PCS3_PORT49;3:[!//
FTM5_FLT1_PORT49;4:[!//
FTM5_FLT1_PORT49;4:[!//
ADC0_SE16_PORT50;0:[!//
ADC0_SE16_PORT50;0:[!//
FTM5_CH7_PORT50;2:[!//
FTM5_CH7_PORT50;2:[!//
LPSPI1_PCS1_PORT50;4:[!//
LPSPI1_PCS1_PORT50;4:[!//
FTM5_CH7_PORT51;2:[!//
ADC0_SE17_PORT52;0:[!//
ADC0_SE17_PORT52;0:[!//
FTM6_CH0_PORT52;2:[!//
ADC0_SE18_PORT53;0:[!//
ADC0_SE18_PORT53;0:[!//
FTM6_CH1_PORT53;2:[!//
ADC0_SE19_PORT54;0:[!//
ADC0_SE19_PORT54;0:[!//
FTM6_CH2_PORT54;2:[!//
MII_CRS_PORT54;3:[!//
LPUART1_TX_PORT54;5:[!//
LPUART1_TX_PORT54;5:[!//
ADC0_SE20_PORT55;0:[!//
ADC0_SE20_PORT55;0:[!//
FTM6_CH3_PORT55;2:[!//
LPUART1_RX_PORT55;3:[!//
LPUART1_RX_PORT55;3:[!//
MII_COL_PORT55;4:[!//
FTM6_CH4_PORT56;2:[!//
ADC0_SE21_PORT57;0:[!//
ADC0_SE21_PORT57;0:[!//
FTM6_CH5_PORT57;2:[!//
LPSPI2_PCS0_PORT57;5:[!//
LPSPI2_PCS0_PORT57;5:[!//
FTM6_CH6_PORT58;2:[!//
ADC0_SE22_PORT59;0:[!//
ADC0_SE22_PORT59;0:[!//
FTM6_CH7_PORT59;2:[!//
LPSPI2_SOUT_PORT59;5:[!//
LPSPI2_SOUT_PORT59;5:[!//
ADC0_SE23_PORT60;0:[!//
ADC0_SE23_PORT60;0:[!//
FTM7_CH0_PORT60;2:[!//
LPSPI2_SIN_PORT60;5:[!//
LPSPI2_SIN_PORT60;5:[!//
ADC0_SE24_PORT61;0:[!//
FTM7_CH1_PORT61;2:[!//
LPSPI2_SCK_PORT61;5:[!//
LPSPI2_SCK_PORT61;5:[!//
FTM7_CH2_PORT62;2:[!//
FTM7_CH3_PORT63;2:[!//
ADC0_SE8_PORT64;0:[!//
FTM0_CH0_PORT64;2:[!//
LPSPI2_SIN_PORT64;3:[!//
LPSPI2_SIN_PORT64;3:[!//
LPSPI2_SIN_PORT64;3:[!//
MII_RMII_RXD_1_PORT64;4:[!//
MII_RMII_RXD_0_PORT64;5:[!//
FTM1_CH6_PORT64;6:[!//
QSPI_B_RWDS_PORT64;7:[!//
ADC0_SE9_PORT65;0:[!//
FTM0_CH1_PORT65;2:[!//
LPSPI2_SOUT_PORT65;3:[!//
LPSPI2_SOUT_PORT65;3:[!//
LPSPI2_SOUT_PORT65;3:[!//
MII_RMII_RXD_1_PORT65;4:[!//
MII_RMII_RXD_0_PORT65;5:[!//
FTM1_CH7_PORT65;6:[!//
QSPI_B_SCK_PORT65;7:[!//
ADC0_SE10_CMP0_IN5_PORT66;0:[!//
FTM0_CH2_PORT66;2:[!//
CAN0_RX_PORT66;3:[!//
LPUART0_RX_PORT66;4:[!//
MII_RMII_TXD_0_PORT66;5:[!//
ETM_TRACE_CLKOUT_PORT66;6:[!//
QSPI_A_IO3_PORT66;7:[!//
ADC0_SE11_CMP0_IN4_PORT67;0:[!//
FTM0_CH3_PORT67;2:[!//
CAN0_TX_PORT67;3:[!//
LPUART0_TX_PORT67;4:[!//
MII_TX_ER_PORT67;5:[!//
QSPI_A_CS_PORT67;6:[!//
QSPI_B_IO3_PORT67;7:[!//
CMP0_IN2_PORT68;0:[!//
FTM1_CH0_PORT68;2:[!//
RTC_CLKOUT_PORT68;3:[!//
EWM_IN_PORT68;5:[!//
EWM_IN_PORT68;5:[!//
EWM_IN_PORT68;5:[!//
EWM_IN_PORT68;5:[!//
FTM1_QD_PHB_PORT68;6:[!//
JTAG_TCLK_SWD_CLK_PORT68;7:[!//
FTM2_CH0_PORT69;2:[!//
FTM2_CH0_PORT69;2:[!//
FTM2_CH0_PORT69;2:[!//
FTM2_CH0_PORT69;2:[!//
RTC_CLKOUT_PORT69;3:[!//
LPI2C1_HREQ_PORT69;4:[!//
FTM2_QD_PHB_PORT69;6:[!//
FTM2_QD_PHB_PORT69;6:[!//
FTM2_QD_PHB_PORT69;6:[!//
FTM2_QD_PHB_PORT69;6:[!//
JTAG_TDI_PORT69;7:[!//
ADC1_SE4_PORT70;0:[!//
ADC1_SE4_PORT70;0:[!//
ADC1_SE4_PORT70;0:[!//
ADC1_SE4_PORT70;0:[!//
LPUART1_RX_PORT70;2:[!//
CAN1_RX_PORT70;3:[!//
CAN1_RX_PORT70;3:[!//
CAN1_RX_PORT70;3:[!//
CAN1_RX_PORT70;3:[!//
FTM3_CH2_PORT70;4:[!//
FTM3_CH2_PORT70;4:[!//
FTM3_CH2_PORT70;4:[!//
FTM3_CH2_PORT70;4:[!//
FTM1_QD_PHB_PORT70;6:[!//
ADC1_SE5_PORT71;0:[!//
ADC1_SE5_PORT71;0:[!//
ADC1_SE5_PORT71;0:[!//
ADC1_SE5_PORT71;0:[!//
LPUART1_TX_PORT71;2:[!//
CAN1_TX_PORT71;3:[!//
CAN1_TX_PORT71;3:[!//
CAN1_TX_PORT71;3:[!//
CAN1_TX_PORT71;3:[!//
FTM3_CH3_PORT71;4:[!//
FTM3_CH3_PORT71;4:[!//
FTM3_CH3_PORT71;4:[!//
FTM3_CH3_PORT71;4:[!//
FTM1_QD_PHA_PORT71;6:[!//
LPUART1_RX_PORT72;2:[!//
FTM1_FLT0_PORT72;3:[!//
FTM5_CH1_PORT72;4:[!//
FTM5_CH1_PORT72;4:[!//
LPUART0_CTS_PORT72;6:[!//
LPUART1_TX_PORT73;2:[!//
FTM1_FLT1_PORT73;3:[!//
FTM5_CH0_PORT73;4:[!//
FTM5_CH0_PORT73;4:[!//
LPUART0_RTS_PORT73;6:[!//
FTM3_CH4_PORT74;2:[!//
FTM3_CH4_PORT74;2:[!//
FTM3_CH4_PORT74;2:[!//
FTM3_CH4_PORT74;2:[!//
TRGMUX_IN11_PORT74;6:[!//
TRGMUX_IN11_PORT74;6:[!//
TRGMUX_IN11_PORT74;6:[!//
TRGMUX_IN11_PORT74;6:[!//
FTM3_CH5_PORT75;2:[!//
FTM3_CH5_PORT75;2:[!//
FTM3_CH5_PORT75;2:[!//
FTM3_CH5_PORT75;2:[!//
FTM4_CH2_PORT75;3:[!//
FTM4_CH2_PORT75;3:[!//
TRGMUX_IN10_PORT75;6:[!//
TRGMUX_IN10_PORT75;6:[!//
TRGMUX_IN10_PORT75;6:[!//
TRGMUX_IN10_PORT75;6:[!//
FTM3_CH6_PORT76;2:[!//
FTM3_CH6_PORT76;2:[!//
FTM3_CH6_PORT76;2:[!//
FTM3_CH6_PORT76;2:[!//
FTM2_CH6_PORT76;3:[!//
FTM2_CH6_PORT76;3:[!//
FTM2_CH6_PORT76;3:[!//
FTM2_CH6_PORT76;3:[!//
LPUART2_CTS_PORT76;4:[!//
LPUART2_CTS_PORT76;4:[!//
LPUART2_CTS_PORT76;4:[!//
FTM3_CH7_PORT77;2:[!//
FTM3_CH7_PORT77;2:[!//
FTM3_CH7_PORT77;2:[!//
FTM3_CH7_PORT77;2:[!//
FTM2_CH7_PORT77;3:[!//
FTM2_CH7_PORT77;3:[!//
FTM2_CH7_PORT77;3:[!//
FTM2_CH7_PORT77;3:[!//
LPUART2_RTS_PORT77;4:[!//
LPUART2_RTS_PORT77;4:[!//
LPUART2_RTS_PORT77;4:[!//
ADC0_SE12_PORT78;0:[!//
FTM1_CH2_PORT78;2:[!//
LPSPI2_PCS0_PORT78;3:[!//
LPSPI2_PCS0_PORT78;3:[!//
LPSPI2_PCS0_PORT78;3:[!//
MII_COL_PORT78;4:[!//
TRGMUX_IN9_PORT78;6:[!//
ADC0_SE13_PORT79;0:[!//
FTM1_CH3_PORT79;2:[!//
LPSPI2_SCK_PORT79;3:[!//
LPSPI2_SCK_PORT79;3:[!//
LPSPI2_SCK_PORT79;3:[!//
MII_CRS_PORT79;4:[!//
TRGMUX_IN8_PORT79;6:[!//
QSPI_B_CS_PORT79;7:[!//
ADC0_SE14_PORT80;0:[!//
FTM1_FLT2_PORT80;2:[!//
CAN2_RX_PORT80;3:[!//
CAN2_RX_PORT80;3:[!//
CAN2_RX_PORT80;3:[!//
LPI2C1_SDAS_PORT80;4:[!//
MII_RMII_RX_ER_PORT80;5:[!//
QSPI_B_IO7_PORT80;7:[!//
ADC0_SE15_PORT81;0:[!//
FTM1_FLT3_PORT81;2:[!//
CAN2_TX_PORT81;3:[!//
CAN2_TX_PORT81;3:[!//
CAN2_TX_PORT81;3:[!//
LPI2C1_SCLS_PORT81;4:[!//
MII_RMII_RX_DV_PORT81;5:[!//
QSPI_B_IO6_PORT81;7:[!//
FTM7_CH4_PORT82;2:[!//
ADC0_SE25_PORT83;0:[!//
FTM7_CH5_PORT83;2:[!//
LPSPI2_PCS1_PORT83;5:[!//
LPSPI2_PCS1_PORT83;5:[!//
FTM7_CH6_PORT84;2:[!//
FTM7_CH7_PORT85;2:[!//
FTM7_FLT0_PORT85;4:[!//
FTM7_FLT1_PORT86;2:[!//
ADC0_SE26_PORT87;0:[!//
LPSPI0_SCK_PORT87;2:[!//
LPSPI0_SCK_PORT87;2:[!//
FTM4_CH0_PORT88;2:[!//
FTM4_CH1_PORT89;2:[!//
FTM4_CH3_PORT90;2:[!//
ADC0_SE27_PORT91;0:[!//
FTM4_CH4_PORT91;2:[!//
FTM4_CH4_PORT91;2:[!//
ADC0_SE28_PORT92;0:[!//
FTM4_CH7_PORT92;2:[!//
FTM4_CH7_PORT92;2:[!//
ADC0_SE29_PORT93;0:[!//
FTM5_CH2_PORT93;2:[!//
FTM5_CH2_PORT93;2:[!//
ADC0_SE30_PORT94;0:[!//
FTM5_CH4_PORT94;2:[!//
FTM5_CH4_PORT94;2:[!//
FXIO_D0_PORT94;3:[!//
FXIO_D0_PORT94;3:[!//
LPI2C1_SDAS_PORT94;4:[!//
ADC0_SE31_PORT95;0:[!//
FTM5_CH6_PORT95;2:[!//
FTM5_CH6_PORT95;2:[!//
FXIO_D1_PORT95;3:[!//
FXIO_D1_PORT95;3:[!//
LPI2C1_SDA_PORT95;4:[!//
FTM0_CH2_PORT96;2:[!//
LPSPI1_SCK_PORT96;3:[!//
FTM2_CH0_PORT96;4:[!//
FTM2_CH0_PORT96;4:[!//
FTM2_CH0_PORT96;4:[!//
FTM2_CH0_PORT96;4:[!//
ETM_TRACE_D0_PORT96;5:[!//
FXIO_D0_PORT96;6:[!//
TRGMUX_OUT1_PORT96;7:[!//
FTM0_CH3_PORT97;2:[!//
LPSPI1_SIN_PORT97;3:[!//
FTM2_CH1_PORT97;4:[!//
FTM2_CH1_PORT97;4:[!//
FTM2_CH1_PORT97;4:[!//
FTM2_CH1_PORT97;4:[!//
SAI0_MCLK_PORT97;5:[!//
FXIO_D1_PORT97;6:[!//
TRGMUX_OUT2_PORT97;7:[!//
ADC1_SE2_PORT98;0:[!//
ADC1_SE2_PORT98;0:[!//
ADC1_SE2_PORT98;0:[!//
ADC1_SE2_PORT98;0:[!//
FTM3_CH4_PORT98;2:[!//
FTM3_CH4_PORT98;2:[!//
FTM3_CH4_PORT98;2:[!//
FTM3_CH4_PORT98;2:[!//
LPSPI1_SOUT_PORT98;3:[!//
FXIO_D4_PORT98;4:[!//
FXIO_D6_PORT98;5:[!//
TRGMUX_IN5_PORT98;6:[!//
ADC1_SE3_PORT99;0:[!//
ADC1_SE3_PORT99;0:[!//
ADC1_SE3_PORT99;0:[!//
ADC1_SE3_PORT99;0:[!//
FTM3_CH5_PORT99;2:[!//
FTM3_CH5_PORT99;2:[!//
FTM3_CH5_PORT99;2:[!//
FTM3_CH5_PORT99;2:[!//
LPSPI1_PCS0_PORT99;3:[!//
FXIO_D5_PORT99;4:[!//
FXIO_D7_PORT99;5:[!//
TRGMUX_IN4_PORT99;6:[!//
NMI_b_PORT99;7:[!//
ADC1_SE6_PORT100;0:[!//
ADC1_SE6_PORT100;0:[!//
ADC1_SE6_PORT100;0:[!//
ADC1_SE6_PORT100;0:[!//
FTM0_FLT3_PORT100;2:[!//
FTM3_FLT3_PORT100;3:[!//
FTM3_FLT3_PORT100;3:[!//
FTM3_FLT3_PORT100;3:[!//
FTM3_FLT3_PORT100;3:[!//
FTM2_CH3_PORT101;2:[!//
FTM2_CH3_PORT101;2:[!//
FTM2_CH3_PORT101;2:[!//
FTM2_CH3_PORT101;2:[!//
LPTMR0_ALT2_PORT101;3:[!//
FTM2_FLT1_PORT101;4:[!//
FTM2_FLT1_PORT101;4:[!//
FTM2_FLT1_PORT101;4:[!//
FTM2_FLT1_PORT101;4:[!//
MII_TXD3_PORT101;5:[!//
TRGMUX_IN7_PORT101;6:[!//
QSPI_B_IO2_PORT101;7:[!//
CMP0_IN7_PORT102;0:[!//
LPUART2_RX_PORT102;2:[!//
LPUART2_RX_PORT102;2:[!//
LPUART2_RX_PORT102;2:[!//
FTM2_FLT2_PORT102;4:[!//
FTM2_FLT2_PORT102;4:[!//
FTM2_FLT2_PORT102;4:[!//
FTM2_FLT2_PORT102;4:[!//
MII_TXD2_PORT102;5:[!//
QSPI_B_IO1_PORT102;7:[!//
CMP0_IN6_PORT103;0:[!//
LPUART2_TX_PORT103;2:[!//
LPUART2_TX_PORT103;2:[!//
LPUART2_TX_PORT103;2:[!//
FTM2_FLT3_PORT103;4:[!//
FTM2_FLT3_PORT103;4:[!//
FTM2_FLT3_PORT103;4:[!//
FTM2_FLT3_PORT103;4:[!//
MII_RMII_TXD_1_PORT103;5:[!//
ETM_TRACE_D0_PORT103;6:[!//
QSPI_A_IO1_PORT103;7:[!//
LPI2C1_SDA_PORT104;2:[!//
MII_RXD3_PORT104;3:[!//
FTM2_FLT2_PORT104;4:[!//
FTM2_FLT2_PORT104;4:[!//
FTM2_FLT2_PORT104;4:[!//
FTM2_FLT2_PORT104;4:[!//
FXIO_D1_PORT104;5:[!//
FXIO_D1_PORT104;5:[!//
FXIO_D1_PORT104;5:[!//
FXIO_D1_PORT104;5:[!//
FTM1_CH4_PORT104;6:[!//
FTM1_CH4_PORT104;6:[!//
FTM1_CH4_PORT104;6:[!//
FTM1_CH4_PORT104;6:[!//
QSPI_B_IO5_PORT104;7:[!//
LPI2C1_SCL_PORT105;2:[!//
FXIO_D0_PORT105;3:[!//
FXIO_D0_PORT105;3:[!//
FXIO_D0_PORT105;3:[!//
FXIO_D0_PORT105;3:[!//
FTM2_FLT3_PORT105;4:[!//
FTM2_FLT3_PORT105;4:[!//
FTM2_FLT3_PORT105;4:[!//
FTM2_FLT3_PORT105;4:[!//
MII_RXD2_PORT105;5:[!//
FTM1_CH5_PORT105;6:[!//
FTM1_CH5_PORT105;6:[!//
FTM1_CH5_PORT105;6:[!//
FTM1_CH5_PORT105;6:[!//
QSPI_B_IO4_PORT105;7:[!//
FTM2_CH0_PORT106;2:[!//
FTM2_CH0_PORT106;2:[!//
FTM2_CH0_PORT106;2:[!//
FTM2_CH0_PORT106;2:[!//
FTM2_QD_PHB_PORT106;3:[!//
FTM2_QD_PHB_PORT106;3:[!//
FTM2_QD_PHB_PORT106;3:[!//
FTM2_QD_PHB_PORT106;3:[!//
ETM_TRACE_D3_PORT106;4:[!//
MII_RX_CLK_PORT106;5:[!//
CLKOUT_PORT106;6:[!//
CLKOUT_PORT106;6:[!//
QSPI_A_SCK_PORT106;7:[!//
FTM2_CH1_PORT107;2:[!//
FTM2_CH1_PORT107;2:[!//
FTM2_CH1_PORT107;2:[!//
FTM2_CH1_PORT107;2:[!//
FTM2_QD_PHA_PORT107;3:[!//
FTM2_QD_PHA_PORT107;3:[!//
FTM2_QD_PHA_PORT107;3:[!//
FTM2_QD_PHA_PORT107;3:[!//
ETM_TRACE_D2_PORT107;4:[!//
MII_RMII_TX_CLK_PORT107;5:[!//
LPUART2_CTS_PORT107;6:[!//
LPUART2_CTS_PORT107;6:[!//
LPUART2_CTS_PORT107;6:[!//
QSPI_A_IO0_PORT107;7:[!//
FTM2_CH2_PORT108;2:[!//
FTM2_CH2_PORT108;2:[!//
FTM2_CH2_PORT108;2:[!//
FTM2_CH2_PORT108;2:[!//
LPI2C1_HREQ_PORT108;3:[!//
ETM_TRACE_D1_PORT108;4:[!//
MII_RMII_TX_EN_PORT108;5:[!//
LPUART2_RTS_PORT108;6:[!//
LPUART2_RTS_PORT108;6:[!//
LPUART2_RTS_PORT108;6:[!//
QSPI_A_IO2_PORT108;7:[!//
FTM2_CH4_PORT109;2:[!//
FTM2_CH4_PORT109;2:[!//
FTM2_CH4_PORT109;2:[!//
FTM2_CH4_PORT109;2:[!//
LPUART1_RX_PORT109;3:[!//
LPUART1_RX_PORT109;3:[!//
LPUART1_RX_PORT109;3:[!//
LPUART1_RX_PORT109;3:[!//
ENET_TMR1_PORT109;5:[!//
RTC_CLKOUT_PORT109;7:[!//
RTC_CLKOUT_PORT109;7:[!//
RTC_CLKOUT_PORT109;7:[!//
RTC_CLKOUT_PORT109;7:[!//
FTM2_CH5_PORT110;2:[!//
FTM2_CH5_PORT110;2:[!//
FTM2_CH5_PORT110;2:[!//
FTM2_CH5_PORT110;2:[!//
LPUART1_TX_PORT110;3:[!//
LPUART1_TX_PORT110;3:[!//
LPUART1_TX_PORT110;3:[!//
LPUART1_TX_PORT110;3:[!//
ENET_TMR0_PORT110;5:[!//
CLKOUT_PORT110;7:[!//
CLKOUT_PORT110;7:[!//
CLKOUT_PORT110;7:[!//
CLKOUT_PORT110;7:[!//
FTM0_CH0_PORT111;2:[!//
ETM_TRACE_D3_PORT111;3:[!//
LPSPI0_SCK_PORT111;4:[!//
ENET_TMR2_PORT111;5:[!//
FTM0_CH1_PORT112;2:[!//
ETM_TRACE_D2_PORT112;3:[!//
LPSPI0_SIN_PORT112;4:[!//
CMP0_RRT_PORT112;5:[!//
ETM_TRACE_CLKOUT_PORT112;6:[!//
FTM0_FLT2_PORT113;2:[!//
FTM0_FLT2_PORT113;2:[!//
FTM0_FLT2_PORT113;2:[!//
FTM0_FLT2_PORT113;2:[!//
LPUART2_RX_PORT113;3:[!//
LPUART2_RX_PORT113;3:[!//
LPUART2_RX_PORT113;3:[!//
FTM5_FLT1_PORT113;4:[!//
FTM5_FLT1_PORT113;4:[!//
ADC1_SE16_PORT114;0:[!//
ADC1_SE16_PORT114;0:[!//
FTM5_CH7_PORT114;2:[!//
FTM5_CH7_PORT114;2:[!//
FXIO_D2_PORT114;3:[!//
FXIO_D2_PORT114;3:[!//
LPI2C1_SCLS_PORT114;4:[!//
ADC1_SE17_PORT115;0:[!//
ADC1_SE17_PORT115;0:[!//
FTM6_CH0_PORT115;2:[!//
FXIO_D3_PORT115;3:[!//
FXIO_D3_PORT115;3:[!//
LPI2C1_SCL_PORT115;4:[!//
FTM6_CH1_PORT116;2:[!//
FTM6_CH2_PORT117;2:[!//
ADC1_SE18_PORT118;0:[!//
ADC1_SE18_PORT118;0:[!//
FTM6_CH3_PORT118;2:[!//
ADC1_SE19_PORT119;0:[!//
ADC1_SE19_PORT119;0:[!//
FTM6_CH4_PORT119;2:[!//
ADC1_SE20_PORT120;0:[!//
ADC1_SE20_PORT120;0:[!//
FTM6_CH5_PORT120;2:[!//
FTM6_CH6_PORT121;2:[!//
FTM6_CH7_PORT122;2:[!//
FXIO_D7_PORT122;3:[!//
ADC1_SE21_PORT123;0:[!//
ADC1_SE21_PORT123;0:[!//
FTM7_CH0_PORT123;2:[!//
ADC1_SE22_PORT124;0:[!//
ADC1_SE22_PORT124;0:[!//
FTM7_CH1_PORT124;2:[!//
ADC1_SE23_PORT125;0:[!//
ADC1_SE23_PORT125;0:[!//
FTM7_CH2_PORT125;2:[!//
ADC1_SE24_PORT126;0:[!//
FTM7_CH3_PORT126;2:[!//
FTM6_FLT1_PORT126;3:[!//
FTM7_CH4_PORT127;2:[!//
FXIO_D6_PORT127;3:[!//
FTM6_FLT0_PORT127;5:[!//
LPSPI0_SCK_PORT128;2:[!//
TCLK1_PORT128;3:[!//
LPI2C1_SDA_PORT128;4:[!//
LPSPI1_SOUT_PORT128;5:[!//
FTM1_FLT2_PORT128;6:[!//
SAI0_D2_PORT128;7:[!//
LPSPI0_SIN_PORT129;2:[!//
LPI2C0_HREQ_PORT129;3:[!//
LPI2C1_SCL_PORT129;4:[!//
LPSPI1_PCS0_PORT129;5:[!//
FTM1_FLT1_PORT129;6:[!//
SAI0_D1_PORT129;7:[!//
ADC1_SE10_PORT130;0:[!//
ADC1_SE10_PORT130;0:[!//
ADC1_SE10_PORT130;0:[!//
ADC1_SE10_PORT130;0:[!//
LPSPI0_SOUT_PORT130;2:[!//
LPTMR0_ALT3_PORT130;3:[!//
FTM3_CH6_PORT130;4:[!//
FTM3_CH6_PORT130;4:[!//
FTM3_CH6_PORT130;4:[!//
FTM3_CH6_PORT130;4:[!//
LPUART1_CTS_PORT130;6:[!//
SAI1_SYNC_PORT130;7:[!//
FTM0_FLT0_PORT131;2:[!//
LPUART2_RTS_PORT131;3:[!//
LPUART2_RTS_PORT131;3:[!//
LPUART2_RTS_PORT131;3:[!//
FTM2_FLT0_PORT131;4:[!//
FTM2_FLT0_PORT131;4:[!//
FTM2_FLT0_PORT131;4:[!//
FTM2_FLT0_PORT131;4:[!//
TRGMUX_IN6_PORT131;6:[!//
CMP0_OUT_PORT131;7:[!//
ETM_TRACE_D1_PORT132;2:[!//
FTM2_QD_PHB_PORT132;3:[!//
FTM2_QD_PHB_PORT132;3:[!//
FTM2_QD_PHB_PORT132;3:[!//
FTM2_QD_PHB_PORT132;3:[!//
FTM2_CH2_PORT132;4:[!//
FTM2_CH2_PORT132;4:[!//
FTM2_CH2_PORT132;4:[!//
FTM2_CH2_PORT132;4:[!//
CAN0_RX_PORT132;5:[!//
FXIO_D6_PORT132;6:[!//
EWM_OUT_b_PORT132;7:[!//
EWM_OUT_b_PORT132;7:[!//
EWM_OUT_b_PORT132;7:[!//
EWM_OUT_b_PORT132;7:[!//
TCLK2_PORT133;2:[!//
FTM2_QD_PHA_PORT133;3:[!//
FTM2_QD_PHA_PORT133;3:[!//
FTM2_QD_PHA_PORT133;3:[!//
FTM2_QD_PHA_PORT133;3:[!//
FTM2_CH3_PORT133;4:[!//
FTM2_CH3_PORT133;4:[!//
FTM2_CH3_PORT133;4:[!//
FTM2_CH3_PORT133;4:[!//
CAN0_TX_PORT133;5:[!//
FXIO_D7_PORT133;6:[!//
EWM_IN_PORT133;7:[!//
EWM_IN_PORT133;7:[!//
EWM_IN_PORT133;7:[!//
EWM_IN_PORT133;7:[!//
ADC1_SE11_PORT134;0:[!//
ADC1_SE11_PORT134;0:[!//
ADC1_SE11_PORT134;0:[!//
ADC1_SE11_PORT134;0:[!//
LPSPI0_PCS2_PORT134;2:[!//
FTM7_FLT1_PORT134;3:[!//
FTM3_CH7_PORT134;4:[!//
FTM3_CH7_PORT134;4:[!//
FTM3_CH7_PORT134;4:[!//
FTM3_CH7_PORT134;4:[!//
LPUART1_RTS_PORT134;6:[!//
FTM0_CH7_PORT135;2:[!//
FTM3_FLT0_PORT135;3:[!//
FTM3_FLT0_PORT135;3:[!//
FTM3_FLT0_PORT135;3:[!//
FTM3_FLT0_PORT135;3:[!//
CMP0_IN3_PORT136;0:[!//
FTM0_CH6_PORT136;2:[!//
MII_RMII_MDC_PORT136;5:[!//
FTM0_CH7_PORT137;2:[!//
LPUART2_CTS_PORT137;3:[!//
LPUART2_CTS_PORT137;3:[!//
LPUART2_CTS_PORT137;3:[!//
ENET_TMR3_PORT137;5:[!//
CLKOUT_PORT138;2:[!//
LPSPI2_PCS1_PORT138;3:[!//
LPSPI2_PCS1_PORT138;3:[!//
LPSPI2_PCS1_PORT138;3:[!//
FTM2_CH4_PORT138;4:[!//
FTM2_CH4_PORT138;4:[!//
FTM2_CH4_PORT138;4:[!//
FTM2_CH4_PORT138;4:[!//
FXIO_D4_PORT138;6:[!//
TRGMUX_OUT4_PORT138;7:[!//
LPSPI2_PCS0_PORT139;2:[!//
LPSPI2_PCS0_PORT139;2:[!//
LPSPI2_PCS0_PORT139;2:[!//
LPTMR0_ALT1_PORT139;3:[!//
FTM2_CH5_PORT139;4:[!//
FTM2_CH5_PORT139;4:[!//
FTM2_CH5_PORT139;4:[!//
FTM2_CH5_PORT139;4:[!//
FXIO_D5_PORT139;6:[!//
TRGMUX_OUT5_PORT139;7:[!//
FTM0_FLT3_PORT140;2:[!//
FTM0_FLT3_PORT140;2:[!//
FTM0_FLT3_PORT140;2:[!//
FTM0_FLT3_PORT140;2:[!//
LPUART2_TX_PORT140;3:[!//
LPUART2_TX_PORT140;3:[!//
LPUART2_TX_PORT140;3:[!//
FTM5_FLT0_PORT140;4:[!//
FTM5_FLT0_PORT140;4:[!//
FTM4_CH5_PORT141;2:[!//
FTM4_CH5_PORT141;2:[!//
LPSPI2_PCS2_PORT141;3:[!//
LPSPI2_PCS2_PORT141;3:[!//
LPSPI2_PCS2_PORT141;3:[!//
FTM2_FLT0_PORT141;4:[!//
FTM2_FLT0_PORT141;4:[!//
FTM2_FLT0_PORT141;4:[!//
FTM2_FLT0_PORT141;4:[!//
FTM0_FLT1_PORT142;2:[!//
FTM0_FLT1_PORT142;2:[!//
FTM0_FLT1_PORT142;2:[!//
FTM0_FLT1_PORT142;2:[!//
FTM2_FLT1_PORT142;4:[!//
FTM2_FLT1_PORT142;4:[!//
FTM2_FLT1_PORT142;4:[!//
FTM2_FLT1_PORT142;4:[!//
LPUART1_CTS_PORT143;2:[!//
LPUART1_CTS_PORT143;2:[!//
LPUART1_CTS_PORT143;2:[!//
LPUART1_CTS_PORT143;2:[!//
LPSPI2_SCK_PORT143;3:[!//
LPSPI2_SCK_PORT143;3:[!//
LPSPI2_SCK_PORT143;3:[!//
FTM2_CH6_PORT143;4:[!//
FTM2_CH6_PORT143;4:[!//
FTM2_CH6_PORT143;4:[!//
FTM2_CH6_PORT143;4:[!//
FTM4_FLT1_PORT143;5:[!//
FTM4_FLT1_PORT143;5:[!//
FXIO_D2_PORT143;6:[!//
FXIO_D2_PORT143;6:[!//
FXIO_D2_PORT143;6:[!//
FXIO_D2_PORT143;6:[!//
TRGMUX_OUT6_PORT143;7:[!//
TRGMUX_OUT6_PORT143;7:[!//
TRGMUX_OUT6_PORT143;7:[!//
TRGMUX_OUT6_PORT143;7:[!//
LPUART1_RTS_PORT144;2:[!//
LPUART1_RTS_PORT144;2:[!//
LPUART1_RTS_PORT144;2:[!//
LPUART1_RTS_PORT144;2:[!//
LPSPI2_SIN_PORT144;3:[!//
LPSPI2_SIN_PORT144;3:[!//
LPSPI2_SIN_PORT144;3:[!//
FTM2_CH7_PORT144;4:[!//
FTM2_CH7_PORT144;4:[!//
FTM2_CH7_PORT144;4:[!//
FTM2_CH7_PORT144;4:[!//
FTM4_FLT0_PORT144;5:[!//
FTM4_FLT0_PORT144;5:[!//
FXIO_D3_PORT144;6:[!//
FXIO_D3_PORT144;6:[!//
FXIO_D3_PORT144;6:[!//
FXIO_D3_PORT144;6:[!//
TRGMUX_OUT7_PORT144;7:[!//
TRGMUX_OUT7_PORT144;7:[!//
TRGMUX_OUT7_PORT144;7:[!//
TRGMUX_OUT7_PORT144;7:[!//
FTM7_CH5_PORT145;2:[!//
FXIO_D5_PORT145;3:[!//
FTM7_CH6_PORT146;2:[!//
FXIO_D4_PORT146;3:[!//
ADC1_SE25_PORT147;0:[!//
FTM7_CH7_PORT147;2:[!//
ADC1_SE26_PORT148;0:[!//
FTM4_CH0_PORT148;2:[!//
FTM4_CH0_PORT148;2:[!//
ADC1_SE27_PORT149;0:[!//
FTM4_CH1_PORT149;2:[!//
FTM4_CH1_PORT149;2:[!//
ADC1_SE28_PORT150;0:[!//
FTM4_CH2_PORT150;2:[!//
FTM4_CH2_PORT150;2:[!//
ADC1_SE29_PORT151;0:[!//
FTM4_CH3_PORT151;2:[!//
FTM4_CH3_PORT151;2:[!//
ADC1_SE30_PORT152;0:[!//
FTM4_CH4_PORT152;2:[!//
FTM4_CH4_PORT152;2:[!//
CAN2_TX_PORT152;3:[!//
CAN2_TX_PORT152;3:[!//
ADC1_SE31_PORT153;0:[!//
FTM4_CH5_PORT153;2:[!//
FTM4_CH5_PORT153;2:[!//
CAN2_RX_PORT153;3:[!//
CAN2_RX_PORT153;3:[!//
FTM4_CH6_PORT154;2:[!//
FTM4_CH7_PORT155;2:[!//
[!ENDVAR!]

[!VAR "PinAbstractionModes_1"!]

#define    PORT0_ADC0_SE0_CMP0_IN0        (PORT_ALT0_FUNC_MODE)
#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT0_FXIO_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT0_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT0_TRGMUX_OUT3        (PORT_ALT7_FUNC_MODE)
#define    PORT1_ADC0_SE1_CMP0_IN1        (PORT_ALT0_FUNC_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT1_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT1_FXIO_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT1_FTM1_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT1_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT1_TRGMUX_OUT0        (PORT_ALT7_FUNC_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_LPI2C0_SDA        (PORT_ALT3_FUNC_MODE)
#define    PORT2_FXIO_D4        (PORT_ALT5_FUNC_MODE)
#define    PORT2_LPUART0_RX        (PORT_ALT6_FUNC_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_LPI2C0_SCL        (PORT_ALT3_FUNC_MODE)
#define    PORT3_FXIO_D5        (PORT_ALT5_FUNC_MODE)
#define    PORT3_LPUART0_TX        (PORT_ALT6_FUNC_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_CMP0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT4_JTAG_TMS_SWD_DIO        (PORT_ALT7_FUNC_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT5_RESET_b        (PORT_ALT7_FUNC_MODE)
#define    PORT7_ADC0_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT7_RTC_CLKIN        (PORT_ALT4_FUNC_MODE)
#define    PORT7_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_FTM1_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT10_FXIO_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT10_JTAG_TDO        (PORT_ALT7_FUNC_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_FTM1_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT11_FXIO_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT11_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_FTM1_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_FTM1_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT32_ADC0_SE4_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_LPUART0_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT32_LPSPI0_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT32_LPTMR0_ALT3        (PORT_ALT4_FUNC_MODE)
#define    PORT32_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT33_ADC0_SE5_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_LPUART0_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT33_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT33_TCLK0        (PORT_ALT4_FUNC_MODE)
#define    PORT33_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT34_ADC0_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT34_LPSPI0_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT34_FTM1_QD_PHB        (PORT_ALT4_FUNC_MODE)
#define    PORT34_TRGMUX_IN3        (PORT_ALT6_FUNC_MODE)
#define    PORT35_ADC0_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT35_LPSPI0_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT35_FTM1_QD_PHA        (PORT_ALT4_FUNC_MODE)
#define    PORT35_TRGMUX_IN2        (PORT_ALT6_FUNC_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT36_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT36_TRGMUX_IN1        (PORT_ALT6_FUNC_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT37_LPSPI0_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT37_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT37_CLKOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT37_TRGMUX_IN0        (PORT_ALT6_FUNC_MODE)
#define    PORT38_XTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LPI2C0_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT39_EXTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_LPI2C0_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT45_ADC1_SE8_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT65_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT65_FTM1_CH7        (PORT_ALT6_FUNC_MODE)
#define    PORT66_ADC0_SE10_CMP0_IN5        (PORT_ALT0_FUNC_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT66_CAN0_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT66_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT67_ADC0_SE11_CMP0_IN4        (PORT_ALT0_FUNC_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT67_CAN0_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT67_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT68_CMP0_IN2        (PORT_ALT0_FUNC_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT68_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT68_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT68_JTAG_TCLK_SWD_CLK        (PORT_ALT7_FUNC_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT69_JTAG_TDI        (PORT_ALT7_FUNC_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT70_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT71_FTM1_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FTM1_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT72_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT73_FTM1_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT73_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT78_ADC0_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT78_TRGMUX_IN9        (PORT_ALT6_FUNC_MODE)
#define    PORT79_ADC0_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT79_TRGMUX_IN8        (PORT_ALT6_FUNC_MODE)
#define    PORT80_ADC0_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_FTM1_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT96_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT96_FXIO_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT96_TRGMUX_OUT1        (PORT_ALT7_FUNC_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT97_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT97_FXIO_D1        (PORT_ALT6_FUNC_MODE)
#define    PORT97_TRGMUX_OUT2        (PORT_ALT7_FUNC_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT98_FXIO_D4        (PORT_ALT4_FUNC_MODE)
#define    PORT98_FXIO_D6        (PORT_ALT5_FUNC_MODE)
#define    PORT98_TRGMUX_IN5        (PORT_ALT6_FUNC_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT99_FXIO_D5        (PORT_ALT4_FUNC_MODE)
#define    PORT99_FXIO_D7        (PORT_ALT5_FUNC_MODE)
#define    PORT99_TRGMUX_IN4        (PORT_ALT6_FUNC_MODE)
#define    PORT99_NMI_b        (PORT_ALT7_FUNC_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_LPTMR0_ALT2        (PORT_ALT3_FUNC_MODE)
#define    PORT101_TRGMUX_IN7        (PORT_ALT6_FUNC_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT111_LPSPI0_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT112_LPSPI0_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT112_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT132_FXIO_D6        (PORT_ALT6_FUNC_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_TCLK2        (PORT_ALT2_FUNC_MODE)
#define    PORT133_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT133_FXIO_D7        (PORT_ALT6_FUNC_MODE)
#define    PORT136_CMP0_IN3        (PORT_ALT0_FUNC_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_2"!]

#define    PORT0_ADC0_SE0_CMP0_IN0        (PORT_ALT0_FUNC_MODE)
#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT0_FXIO_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT0_TRGMUX_OUT3        (PORT_ALT7_FUNC_MODE)
#define    PORT1_ADC0_SE1_CMP0_IN1        (PORT_ALT0_FUNC_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT1_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT1_FXIO_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT1_FTM1_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT1_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT1_TRGMUX_OUT0        (PORT_ALT7_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_LPI2C0_SDA        (PORT_ALT3_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_FXIO_D4        (PORT_ALT5_FUNC_MODE)
#define    PORT2_LPUART0_RX        (PORT_ALT6_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_LPI2C0_SCL        (PORT_ALT3_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_FXIO_D5        (PORT_ALT5_FUNC_MODE)
#define    PORT3_LPUART0_TX        (PORT_ALT6_FUNC_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_CMP0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_JTAG_TMS_SWD_DIO        (PORT_ALT7_FUNC_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT5_RESET_b        (PORT_ALT7_FUNC_MODE)
#define    PORT6_ADC0_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_LPSPI1_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT7_ADC0_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_RTC_CLKIN        (PORT_ALT4_FUNC_MODE)
#define    PORT7_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_FTM1_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT10_FXIO_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT10_JTAG_TDO        (PORT_ALT7_FUNC_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_FTM1_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT11_FXIO_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT11_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT11_SAI0_SYNC        (PORT_ALT6_FUNC_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_FTM1_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_SAI0_BCLK        (PORT_ALT7_FUNC_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_FTM1_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_SAI0_D0        (PORT_ALT7_FUNC_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_SAI0_D3        (PORT_ALT7_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_FTM7_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT18_GPIO        (PORT_GPIO_MODE)
#define    PORT18_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT18_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT18_LPSPI1_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT18_FTM6_CH0        (PORT_ALT5_FUNC_MODE)
#define    PORT19_GPIO        (PORT_GPIO_MODE)
#define    PORT19_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT19_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT19_LPSPI1_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT20_GPIO        (PORT_GPIO_MODE)
#define    PORT20_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT20_LPSPI1_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT21_GPIO        (PORT_GPIO_MODE)
#define    PORT21_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT21_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT21_LPSPI1_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT22_GPIO        (PORT_GPIO_MODE)
#define    PORT22_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT22_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT22_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT23_GPIO        (PORT_GPIO_MODE)
#define    PORT23_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT23_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT24_GPIO        (PORT_GPIO_MODE)
#define    PORT24_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT24_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT32_ADC0_SE4_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_LPUART0_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT32_LPSPI0_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT32_LPTMR0_ALT3        (PORT_ALT4_FUNC_MODE)
#define    PORT32_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT33_ADC0_SE5_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_LPUART0_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT33_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT33_TCLK0        (PORT_ALT4_FUNC_MODE)
#define    PORT33_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT34_ADC0_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT34_LPSPI0_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT34_FTM1_QD_PHB        (PORT_ALT4_FUNC_MODE)
#define    PORT34_TRGMUX_IN3        (PORT_ALT6_FUNC_MODE)
#define    PORT35_ADC0_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT35_LPSPI0_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT35_FTM1_QD_PHA        (PORT_ALT4_FUNC_MODE)
#define    PORT35_TRGMUX_IN2        (PORT_ALT6_FUNC_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT36_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT36_MII_RMII_MDIO        (PORT_ALT5_FUNC_MODE)
#define    PORT36_TRGMUX_IN1        (PORT_ALT6_FUNC_MODE)
#define    PORT36_QSPI_B_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT37_LPSPI0_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT37_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT37_CLKOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT37_TRGMUX_IN0        (PORT_ALT6_FUNC_MODE)
#define    PORT37_MII_RMII_MDC        (PORT_ALT7_FUNC_MODE)
#define    PORT38_XTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LPI2C0_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT39_EXTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_LPI2C0_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_SAI1_BCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_SAI1_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_SAI1_MCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_GPIO        (PORT_GPIO_MODE)
#define    PORT44_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_FTM6_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT45_ADC1_SE8_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT51_GPIO        (PORT_GPIO_MODE)
#define    PORT51_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT54_MII_CRS        (PORT_ALT3_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT56_GPIO        (PORT_GPIO_MODE)
#define    PORT56_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT58_GPIO        (PORT_GPIO_MODE)
#define    PORT58_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT61_ADC0_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT62_GPIO        (PORT_GPIO_MODE)
#define    PORT62_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT63_GPIO        (PORT_GPIO_MODE)
#define    PORT63_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT64_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT64_GPIO        (PORT_GPIO_MODE)
#define    PORT64_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT64_FTM1_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT64_QSPI_B_RWDS        (PORT_ALT7_FUNC_MODE)
#define    PORT65_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT65_FTM1_CH7        (PORT_ALT6_FUNC_MODE)
#define    PORT65_QSPI_B_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT66_ADC0_SE10_CMP0_IN5        (PORT_ALT0_FUNC_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT66_CAN0_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT66_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT66_MII_RMII_TXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT66_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT66_QSPI_A_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT67_ADC0_SE11_CMP0_IN4        (PORT_ALT0_FUNC_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT67_CAN0_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT67_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT67_MII_TX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT67_QSPI_A_CS        (PORT_ALT6_FUNC_MODE)
#define    PORT67_QSPI_B_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT68_CMP0_IN2        (PORT_ALT0_FUNC_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT68_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT68_JTAG_TCLK_SWD_CLK        (PORT_ALT7_FUNC_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT69_LPI2C1_HREQ        (PORT_ALT4_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_JTAG_TDI        (PORT_ALT7_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM1_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FTM1_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT73_FTM1_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT78_ADC0_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT78_TRGMUX_IN9        (PORT_ALT6_FUNC_MODE)
#define    PORT79_ADC0_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_MII_CRS        (PORT_ALT4_FUNC_MODE)
#define    PORT79_TRGMUX_IN8        (PORT_ALT6_FUNC_MODE)
#define    PORT79_QSPI_B_CS        (PORT_ALT7_FUNC_MODE)
#define    PORT80_ADC0_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_FTM1_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT80_MII_RMII_RX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT80_QSPI_B_IO7        (PORT_ALT7_FUNC_MODE)
#define    PORT81_ADC0_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT81_FTM1_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT81_MII_RMII_RX_DV        (PORT_ALT5_FUNC_MODE)
#define    PORT81_QSPI_B_IO6        (PORT_ALT7_FUNC_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT82_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT83_ADC0_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT85_FTM7_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_FTM7_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT87_ADC0_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT91_ADC0_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT92_ADC0_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT93_ADC0_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT94_ADC0_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT95_ADC0_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT96_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_ETM_TRACE_D0        (PORT_ALT5_FUNC_MODE)
#define    PORT96_FXIO_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT96_TRGMUX_OUT1        (PORT_ALT7_FUNC_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT97_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_SAI0_MCLK        (PORT_ALT5_FUNC_MODE)
#define    PORT97_FXIO_D1        (PORT_ALT6_FUNC_MODE)
#define    PORT97_TRGMUX_OUT2        (PORT_ALT7_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT98_FXIO_D4        (PORT_ALT4_FUNC_MODE)
#define    PORT98_FXIO_D6        (PORT_ALT5_FUNC_MODE)
#define    PORT98_TRGMUX_IN5        (PORT_ALT6_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT99_FXIO_D5        (PORT_ALT4_FUNC_MODE)
#define    PORT99_FXIO_D7        (PORT_ALT5_FUNC_MODE)
#define    PORT99_TRGMUX_IN4        (PORT_ALT6_FUNC_MODE)
#define    PORT99_NMI_b        (PORT_ALT7_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_LPTMR0_ALT2        (PORT_ALT3_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_MII_TXD3        (PORT_ALT5_FUNC_MODE)
#define    PORT101_TRGMUX_IN7        (PORT_ALT6_FUNC_MODE)
#define    PORT101_QSPI_B_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT102_CMP0_IN7        (PORT_ALT0_FUNC_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_MII_TXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT102_QSPI_B_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT103_CMP0_IN6        (PORT_ALT0_FUNC_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_MII_RMII_TXD_1        (PORT_ALT5_FUNC_MODE)
#define    PORT103_ETM_TRACE_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT103_QSPI_A_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_LPI2C1_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT104_MII_RXD3        (PORT_ALT3_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_QSPI_B_IO5        (PORT_ALT7_FUNC_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_LPI2C1_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_MII_RXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_QSPI_B_IO4        (PORT_ALT7_FUNC_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_ETM_TRACE_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT106_MII_RX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_QSPI_A_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_ETM_TRACE_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT107_MII_RMII_TX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_QSPI_A_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_LPI2C1_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT108_ETM_TRACE_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT108_MII_RMII_TX_EN        (PORT_ALT5_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_QSPI_A_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_ENET_TMR1        (PORT_ALT5_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_ENET_TMR0        (PORT_ALT5_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT111_ETM_TRACE_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT111_LPSPI0_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT111_ENET_TMR2        (PORT_ALT5_FUNC_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT112_ETM_TRACE_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT112_LPSPI0_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT112_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT112_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT122_FXIO_D7        (PORT_ALT3_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT126_ADC1_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT126_FTM6_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT127_FXIO_D6        (PORT_ALT3_FUNC_MODE)
#define    PORT127_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT128_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT128_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT128_LPSPI1_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT128_FTM1_FLT2        (PORT_ALT6_FUNC_MODE)
#define    PORT128_SAI0_D2        (PORT_ALT7_FUNC_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_LPSPI0_SIN        (PORT_ALT2_FUNC_MODE)
#define    PORT129_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT129_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT129_LPSPI1_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT129_FTM1_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT129_SAI0_D1        (PORT_ALT7_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_LPSPI0_SOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT130_LPTMR0_ALT3        (PORT_ALT3_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT130_SAI1_SYNC        (PORT_ALT7_FUNC_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_TRGMUX_IN6        (PORT_ALT6_FUNC_MODE)
#define    PORT131_CMP0_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_ETM_TRACE_D1        (PORT_ALT2_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT132_FXIO_D6        (PORT_ALT6_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_TCLK2        (PORT_ALT2_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT133_FXIO_D7        (PORT_ALT6_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_LPSPI0_PCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT134_FTM7_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT136_CMP0_IN3        (PORT_ALT0_FUNC_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT136_MII_RMII_MDC        (PORT_ALT5_FUNC_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_ENET_TMR3        (PORT_ALT5_FUNC_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_CLKOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FXIO_D4        (PORT_ALT6_FUNC_MODE)
#define    PORT138_TRGMUX_OUT4        (PORT_ALT7_FUNC_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPTMR0_ALT1        (PORT_ALT3_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FXIO_D5        (PORT_ALT6_FUNC_MODE)
#define    PORT139_TRGMUX_OUT5        (PORT_ALT7_FUNC_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT145_FXIO_D5        (PORT_ALT3_FUNC_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT146_FXIO_D4        (PORT_ALT3_FUNC_MODE)
#define    PORT147_ADC1_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT148_ADC1_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT149_ADC1_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT150_ADC1_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT151_ADC1_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT152_ADC1_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_ADC1_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_3"!]

#define    PORT0_ADC0_SE0_CMP0_IN0        (PORT_ALT0_FUNC_MODE)
#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT0_FXIO_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT0_TRGMUX_OUT3        (PORT_ALT7_FUNC_MODE)
#define    PORT1_ADC0_SE1_CMP0_IN1        (PORT_ALT0_FUNC_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT1_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT1_FXIO_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT1_FTM1_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT1_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT1_TRGMUX_OUT0        (PORT_ALT7_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_LPI2C0_SDA        (PORT_ALT3_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_FXIO_D4        (PORT_ALT5_FUNC_MODE)
#define    PORT2_LPUART0_RX        (PORT_ALT6_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_LPI2C0_SCL        (PORT_ALT3_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_FXIO_D5        (PORT_ALT5_FUNC_MODE)
#define    PORT3_LPUART0_TX        (PORT_ALT6_FUNC_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_CMP0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_JTAG_TMS_SWD_DIO        (PORT_ALT7_FUNC_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT5_RESET_b        (PORT_ALT7_FUNC_MODE)
#define    PORT6_ADC0_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_LPSPI1_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT7_ADC0_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_RTC_CLKIN        (PORT_ALT4_FUNC_MODE)
#define    PORT7_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_FTM1_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT10_FXIO_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT10_JTAG_TDO        (PORT_ALT7_FUNC_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_FTM1_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT11_FXIO_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT11_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT11_SAI0_SYNC        (PORT_ALT6_FUNC_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_FTM1_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_SAI0_BCLK        (PORT_ALT7_FUNC_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_FTM1_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_SAI0_D0        (PORT_ALT7_FUNC_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_SAI0_D3        (PORT_ALT7_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_FTM7_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT18_GPIO        (PORT_GPIO_MODE)
#define    PORT18_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT18_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT18_LPSPI1_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT18_FTM6_CH0        (PORT_ALT5_FUNC_MODE)
#define    PORT19_GPIO        (PORT_GPIO_MODE)
#define    PORT19_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT19_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT19_LPSPI1_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT20_GPIO        (PORT_GPIO_MODE)
#define    PORT20_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT20_LPSPI1_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT21_GPIO        (PORT_GPIO_MODE)
#define    PORT21_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT21_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT21_LPSPI1_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT22_GPIO        (PORT_GPIO_MODE)
#define    PORT22_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT22_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT22_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT23_GPIO        (PORT_GPIO_MODE)
#define    PORT23_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT23_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT24_GPIO        (PORT_GPIO_MODE)
#define    PORT24_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT24_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT32_ADC0_SE4_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_LPUART0_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT32_LPSPI0_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT32_LPTMR0_ALT3        (PORT_ALT4_FUNC_MODE)
#define    PORT32_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT33_ADC0_SE5_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_LPUART0_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT33_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT33_TCLK0        (PORT_ALT4_FUNC_MODE)
#define    PORT33_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT34_ADC0_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT34_LPSPI0_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT34_FTM1_QD_PHB        (PORT_ALT4_FUNC_MODE)
#define    PORT34_TRGMUX_IN3        (PORT_ALT6_FUNC_MODE)
#define    PORT35_ADC0_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT35_LPSPI0_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT35_FTM1_QD_PHA        (PORT_ALT4_FUNC_MODE)
#define    PORT35_TRGMUX_IN2        (PORT_ALT6_FUNC_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT36_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT36_MII_RMII_MDIO        (PORT_ALT5_FUNC_MODE)
#define    PORT36_TRGMUX_IN1        (PORT_ALT6_FUNC_MODE)
#define    PORT36_QSPI_B_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT37_LPSPI0_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT37_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT37_CLKOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT37_TRGMUX_IN0        (PORT_ALT6_FUNC_MODE)
#define    PORT37_MII_RMII_MDC        (PORT_ALT7_FUNC_MODE)
#define    PORT38_XTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LPI2C0_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT39_EXTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_LPI2C0_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_SAI1_BCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_SAI1_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_SAI1_MCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_GPIO        (PORT_GPIO_MODE)
#define    PORT44_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_FTM6_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT45_ADC1_SE8_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT51_GPIO        (PORT_GPIO_MODE)
#define    PORT51_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT54_MII_CRS        (PORT_ALT3_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT56_GPIO        (PORT_GPIO_MODE)
#define    PORT56_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT58_GPIO        (PORT_GPIO_MODE)
#define    PORT58_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT61_ADC0_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT62_GPIO        (PORT_GPIO_MODE)
#define    PORT62_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT63_GPIO        (PORT_GPIO_MODE)
#define    PORT63_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT64_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT64_GPIO        (PORT_GPIO_MODE)
#define    PORT64_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT64_FTM1_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT64_QSPI_B_RWDS        (PORT_ALT7_FUNC_MODE)
#define    PORT65_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT65_FTM1_CH7        (PORT_ALT6_FUNC_MODE)
#define    PORT65_QSPI_B_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT66_ADC0_SE10_CMP0_IN5        (PORT_ALT0_FUNC_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT66_CAN0_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT66_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT66_MII_RMII_TXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT66_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT66_QSPI_A_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT67_ADC0_SE11_CMP0_IN4        (PORT_ALT0_FUNC_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT67_CAN0_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT67_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT67_MII_TX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT67_QSPI_A_CS        (PORT_ALT6_FUNC_MODE)
#define    PORT67_QSPI_B_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT68_CMP0_IN2        (PORT_ALT0_FUNC_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT68_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT68_JTAG_TCLK_SWD_CLK        (PORT_ALT7_FUNC_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT69_LPI2C1_HREQ        (PORT_ALT4_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_JTAG_TDI        (PORT_ALT7_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM1_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FTM1_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT73_FTM1_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT78_ADC0_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT78_TRGMUX_IN9        (PORT_ALT6_FUNC_MODE)
#define    PORT79_ADC0_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_MII_CRS        (PORT_ALT4_FUNC_MODE)
#define    PORT79_TRGMUX_IN8        (PORT_ALT6_FUNC_MODE)
#define    PORT79_QSPI_B_CS        (PORT_ALT7_FUNC_MODE)
#define    PORT80_ADC0_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_FTM1_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT80_MII_RMII_RX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT80_QSPI_B_IO7        (PORT_ALT7_FUNC_MODE)
#define    PORT81_ADC0_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT81_FTM1_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT81_MII_RMII_RX_DV        (PORT_ALT5_FUNC_MODE)
#define    PORT81_QSPI_B_IO6        (PORT_ALT7_FUNC_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT82_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT83_ADC0_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT85_FTM7_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_FTM7_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT87_ADC0_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT91_ADC0_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT92_ADC0_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT93_ADC0_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT94_ADC0_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT95_ADC0_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT96_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_ETM_TRACE_D0        (PORT_ALT5_FUNC_MODE)
#define    PORT96_FXIO_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT96_TRGMUX_OUT1        (PORT_ALT7_FUNC_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT97_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_SAI0_MCLK        (PORT_ALT5_FUNC_MODE)
#define    PORT97_FXIO_D1        (PORT_ALT6_FUNC_MODE)
#define    PORT97_TRGMUX_OUT2        (PORT_ALT7_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT98_FXIO_D4        (PORT_ALT4_FUNC_MODE)
#define    PORT98_FXIO_D6        (PORT_ALT5_FUNC_MODE)
#define    PORT98_TRGMUX_IN5        (PORT_ALT6_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT99_FXIO_D5        (PORT_ALT4_FUNC_MODE)
#define    PORT99_FXIO_D7        (PORT_ALT5_FUNC_MODE)
#define    PORT99_TRGMUX_IN4        (PORT_ALT6_FUNC_MODE)
#define    PORT99_NMI_b        (PORT_ALT7_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_LPTMR0_ALT2        (PORT_ALT3_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_MII_TXD3        (PORT_ALT5_FUNC_MODE)
#define    PORT101_TRGMUX_IN7        (PORT_ALT6_FUNC_MODE)
#define    PORT101_QSPI_B_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT102_CMP0_IN7        (PORT_ALT0_FUNC_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_MII_TXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT102_QSPI_B_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT103_CMP0_IN6        (PORT_ALT0_FUNC_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_MII_RMII_TXD_1        (PORT_ALT5_FUNC_MODE)
#define    PORT103_ETM_TRACE_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT103_QSPI_A_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_LPI2C1_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT104_MII_RXD3        (PORT_ALT3_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_QSPI_B_IO5        (PORT_ALT7_FUNC_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_LPI2C1_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_MII_RXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_QSPI_B_IO4        (PORT_ALT7_FUNC_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_ETM_TRACE_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT106_MII_RX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_QSPI_A_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_ETM_TRACE_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT107_MII_RMII_TX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_QSPI_A_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_LPI2C1_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT108_ETM_TRACE_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT108_MII_RMII_TX_EN        (PORT_ALT5_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_QSPI_A_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_ENET_TMR1        (PORT_ALT5_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_ENET_TMR0        (PORT_ALT5_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT111_ETM_TRACE_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT111_LPSPI0_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT111_ENET_TMR2        (PORT_ALT5_FUNC_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT112_ETM_TRACE_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT112_LPSPI0_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT112_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT112_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT122_FXIO_D7        (PORT_ALT3_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT126_ADC1_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT126_FTM6_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT127_FXIO_D6        (PORT_ALT3_FUNC_MODE)
#define    PORT127_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT128_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT128_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT128_LPSPI1_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT128_FTM1_FLT2        (PORT_ALT6_FUNC_MODE)
#define    PORT128_SAI0_D2        (PORT_ALT7_FUNC_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_LPSPI0_SIN        (PORT_ALT2_FUNC_MODE)
#define    PORT129_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT129_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT129_LPSPI1_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT129_FTM1_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT129_SAI0_D1        (PORT_ALT7_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_LPSPI0_SOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT130_LPTMR0_ALT3        (PORT_ALT3_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT130_SAI1_SYNC        (PORT_ALT7_FUNC_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_TRGMUX_IN6        (PORT_ALT6_FUNC_MODE)
#define    PORT131_CMP0_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_ETM_TRACE_D1        (PORT_ALT2_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT132_FXIO_D6        (PORT_ALT6_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_TCLK2        (PORT_ALT2_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT133_FXIO_D7        (PORT_ALT6_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_LPSPI0_PCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT134_FTM7_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT136_CMP0_IN3        (PORT_ALT0_FUNC_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT136_MII_RMII_MDC        (PORT_ALT5_FUNC_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_ENET_TMR3        (PORT_ALT5_FUNC_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_CLKOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FXIO_D4        (PORT_ALT6_FUNC_MODE)
#define    PORT138_TRGMUX_OUT4        (PORT_ALT7_FUNC_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPTMR0_ALT1        (PORT_ALT3_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FXIO_D5        (PORT_ALT6_FUNC_MODE)
#define    PORT139_TRGMUX_OUT5        (PORT_ALT7_FUNC_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT145_FXIO_D5        (PORT_ALT3_FUNC_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT146_FXIO_D4        (PORT_ALT3_FUNC_MODE)
#define    PORT147_ADC1_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT148_ADC1_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT149_ADC1_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT150_ADC1_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT151_ADC1_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT152_ADC1_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_ADC1_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_4"!]

#define    PORT0_ADC0_SE0_CMP0_IN0        (PORT_ALT0_FUNC_MODE)
#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT0_FXIO_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT0_TRGMUX_OUT3        (PORT_ALT7_FUNC_MODE)
#define    PORT1_ADC0_SE1_CMP0_IN1        (PORT_ALT0_FUNC_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT1_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT1_FXIO_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT1_FTM1_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT1_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT1_TRGMUX_OUT0        (PORT_ALT7_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_LPI2C0_SDA        (PORT_ALT3_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_FXIO_D4        (PORT_ALT5_FUNC_MODE)
#define    PORT2_LPUART0_RX        (PORT_ALT6_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_LPI2C0_SCL        (PORT_ALT3_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_FXIO_D5        (PORT_ALT5_FUNC_MODE)
#define    PORT3_LPUART0_TX        (PORT_ALT6_FUNC_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_CMP0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_JTAG_TMS_SWD_DIO        (PORT_ALT7_FUNC_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT5_RESET_b        (PORT_ALT7_FUNC_MODE)
#define    PORT6_ADC0_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_LPSPI1_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT7_ADC0_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_RTC_CLKIN        (PORT_ALT4_FUNC_MODE)
#define    PORT7_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_FTM1_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT10_FXIO_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT10_JTAG_TDO        (PORT_ALT7_FUNC_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_FTM1_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT11_FXIO_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT11_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT11_SAI0_SYNC        (PORT_ALT6_FUNC_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_FTM1_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_SAI0_BCLK        (PORT_ALT7_FUNC_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_FTM1_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_SAI0_D0        (PORT_ALT7_FUNC_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_SAI0_D3        (PORT_ALT7_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_FTM7_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT18_GPIO        (PORT_GPIO_MODE)
#define    PORT18_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT18_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT18_LPSPI1_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT18_FTM6_CH0        (PORT_ALT5_FUNC_MODE)
#define    PORT19_GPIO        (PORT_GPIO_MODE)
#define    PORT19_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT19_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT19_LPSPI1_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT20_GPIO        (PORT_GPIO_MODE)
#define    PORT20_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT20_LPSPI1_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT21_GPIO        (PORT_GPIO_MODE)
#define    PORT21_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT21_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT21_LPSPI1_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT22_GPIO        (PORT_GPIO_MODE)
#define    PORT22_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT22_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT22_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT23_GPIO        (PORT_GPIO_MODE)
#define    PORT23_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT23_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT24_GPIO        (PORT_GPIO_MODE)
#define    PORT24_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT24_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT32_ADC0_SE4_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_LPUART0_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT32_LPSPI0_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT32_LPTMR0_ALT3        (PORT_ALT4_FUNC_MODE)
#define    PORT32_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT33_ADC0_SE5_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_LPUART0_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT33_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT33_TCLK0        (PORT_ALT4_FUNC_MODE)
#define    PORT33_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT34_ADC0_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT34_LPSPI0_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT34_FTM1_QD_PHB        (PORT_ALT4_FUNC_MODE)
#define    PORT34_TRGMUX_IN3        (PORT_ALT6_FUNC_MODE)
#define    PORT35_ADC0_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT35_LPSPI0_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT35_FTM1_QD_PHA        (PORT_ALT4_FUNC_MODE)
#define    PORT35_TRGMUX_IN2        (PORT_ALT6_FUNC_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT36_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT36_MII_RMII_MDIO        (PORT_ALT5_FUNC_MODE)
#define    PORT36_TRGMUX_IN1        (PORT_ALT6_FUNC_MODE)
#define    PORT36_QSPI_B_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT37_LPSPI0_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT37_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT37_CLKOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT37_TRGMUX_IN0        (PORT_ALT6_FUNC_MODE)
#define    PORT37_MII_RMII_MDC        (PORT_ALT7_FUNC_MODE)
#define    PORT38_XTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LPI2C0_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT39_EXTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_LPI2C0_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_SAI1_BCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_SAI1_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_SAI1_MCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_GPIO        (PORT_GPIO_MODE)
#define    PORT44_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_FTM6_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT45_ADC1_SE8_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT51_GPIO        (PORT_GPIO_MODE)
#define    PORT51_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT54_MII_CRS        (PORT_ALT3_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT56_GPIO        (PORT_GPIO_MODE)
#define    PORT56_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT58_GPIO        (PORT_GPIO_MODE)
#define    PORT58_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT61_ADC0_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT62_GPIO        (PORT_GPIO_MODE)
#define    PORT62_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT63_GPIO        (PORT_GPIO_MODE)
#define    PORT63_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT64_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT64_GPIO        (PORT_GPIO_MODE)
#define    PORT64_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT64_FTM1_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT64_QSPI_B_RWDS        (PORT_ALT7_FUNC_MODE)
#define    PORT65_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT65_FTM1_CH7        (PORT_ALT6_FUNC_MODE)
#define    PORT65_QSPI_B_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT66_ADC0_SE10_CMP0_IN5        (PORT_ALT0_FUNC_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT66_CAN0_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT66_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT66_MII_RMII_TXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT66_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT66_QSPI_A_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT67_ADC0_SE11_CMP0_IN4        (PORT_ALT0_FUNC_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT67_CAN0_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT67_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT67_MII_TX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT67_QSPI_A_CS        (PORT_ALT6_FUNC_MODE)
#define    PORT67_QSPI_B_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT68_CMP0_IN2        (PORT_ALT0_FUNC_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT68_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT68_JTAG_TCLK_SWD_CLK        (PORT_ALT7_FUNC_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT69_LPI2C1_HREQ        (PORT_ALT4_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_JTAG_TDI        (PORT_ALT7_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM1_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FTM1_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT73_FTM1_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT78_ADC0_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT78_TRGMUX_IN9        (PORT_ALT6_FUNC_MODE)
#define    PORT79_ADC0_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_MII_CRS        (PORT_ALT4_FUNC_MODE)
#define    PORT79_TRGMUX_IN8        (PORT_ALT6_FUNC_MODE)
#define    PORT79_QSPI_B_CS        (PORT_ALT7_FUNC_MODE)
#define    PORT80_ADC0_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_FTM1_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT80_MII_RMII_RX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT80_QSPI_B_IO7        (PORT_ALT7_FUNC_MODE)
#define    PORT81_ADC0_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT81_FTM1_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT81_MII_RMII_RX_DV        (PORT_ALT5_FUNC_MODE)
#define    PORT81_QSPI_B_IO6        (PORT_ALT7_FUNC_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT82_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT83_ADC0_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT85_FTM7_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_FTM7_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT87_ADC0_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT91_ADC0_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT92_ADC0_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT93_ADC0_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT94_ADC0_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT95_ADC0_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT96_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_ETM_TRACE_D0        (PORT_ALT5_FUNC_MODE)
#define    PORT96_FXIO_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT96_TRGMUX_OUT1        (PORT_ALT7_FUNC_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT97_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_SAI0_MCLK        (PORT_ALT5_FUNC_MODE)
#define    PORT97_FXIO_D1        (PORT_ALT6_FUNC_MODE)
#define    PORT97_TRGMUX_OUT2        (PORT_ALT7_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT98_FXIO_D4        (PORT_ALT4_FUNC_MODE)
#define    PORT98_FXIO_D6        (PORT_ALT5_FUNC_MODE)
#define    PORT98_TRGMUX_IN5        (PORT_ALT6_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT99_FXIO_D5        (PORT_ALT4_FUNC_MODE)
#define    PORT99_FXIO_D7        (PORT_ALT5_FUNC_MODE)
#define    PORT99_TRGMUX_IN4        (PORT_ALT6_FUNC_MODE)
#define    PORT99_NMI_b        (PORT_ALT7_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_LPTMR0_ALT2        (PORT_ALT3_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_MII_TXD3        (PORT_ALT5_FUNC_MODE)
#define    PORT101_TRGMUX_IN7        (PORT_ALT6_FUNC_MODE)
#define    PORT101_QSPI_B_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT102_CMP0_IN7        (PORT_ALT0_FUNC_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_MII_TXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT102_QSPI_B_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT103_CMP0_IN6        (PORT_ALT0_FUNC_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_MII_RMII_TXD_1        (PORT_ALT5_FUNC_MODE)
#define    PORT103_ETM_TRACE_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT103_QSPI_A_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_LPI2C1_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT104_MII_RXD3        (PORT_ALT3_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_QSPI_B_IO5        (PORT_ALT7_FUNC_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_LPI2C1_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_MII_RXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_QSPI_B_IO4        (PORT_ALT7_FUNC_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_ETM_TRACE_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT106_MII_RX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_QSPI_A_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_ETM_TRACE_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT107_MII_RMII_TX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_QSPI_A_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_LPI2C1_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT108_ETM_TRACE_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT108_MII_RMII_TX_EN        (PORT_ALT5_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_QSPI_A_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_ENET_TMR1        (PORT_ALT5_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_ENET_TMR0        (PORT_ALT5_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT111_ETM_TRACE_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT111_LPSPI0_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT111_ENET_TMR2        (PORT_ALT5_FUNC_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT112_ETM_TRACE_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT112_LPSPI0_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT112_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT112_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT122_FXIO_D7        (PORT_ALT3_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT126_ADC1_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT126_FTM6_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT127_FXIO_D6        (PORT_ALT3_FUNC_MODE)
#define    PORT127_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT128_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT128_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT128_LPSPI1_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT128_FTM1_FLT2        (PORT_ALT6_FUNC_MODE)
#define    PORT128_SAI0_D2        (PORT_ALT7_FUNC_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_LPSPI0_SIN        (PORT_ALT2_FUNC_MODE)
#define    PORT129_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT129_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT129_LPSPI1_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT129_FTM1_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT129_SAI0_D1        (PORT_ALT7_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_LPSPI0_SOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT130_LPTMR0_ALT3        (PORT_ALT3_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT130_SAI1_SYNC        (PORT_ALT7_FUNC_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_TRGMUX_IN6        (PORT_ALT6_FUNC_MODE)
#define    PORT131_CMP0_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_ETM_TRACE_D1        (PORT_ALT2_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT132_FXIO_D6        (PORT_ALT6_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_TCLK2        (PORT_ALT2_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT133_FXIO_D7        (PORT_ALT6_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_LPSPI0_PCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT134_FTM7_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT136_CMP0_IN3        (PORT_ALT0_FUNC_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT136_MII_RMII_MDC        (PORT_ALT5_FUNC_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_ENET_TMR3        (PORT_ALT5_FUNC_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_CLKOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FXIO_D4        (PORT_ALT6_FUNC_MODE)
#define    PORT138_TRGMUX_OUT4        (PORT_ALT7_FUNC_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPTMR0_ALT1        (PORT_ALT3_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FXIO_D5        (PORT_ALT6_FUNC_MODE)
#define    PORT139_TRGMUX_OUT5        (PORT_ALT7_FUNC_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT145_FXIO_D5        (PORT_ALT3_FUNC_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT146_FXIO_D4        (PORT_ALT3_FUNC_MODE)
#define    PORT147_ADC1_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT148_ADC1_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT149_ADC1_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT150_ADC1_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT151_ADC1_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT152_ADC1_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_ADC1_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_5"!]

#define    PORT0_ADC0_SE0_CMP0_IN0        (PORT_ALT0_FUNC_MODE)
#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT0_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT0_FXIO_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_FTM2_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT0_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT0_TRGMUX_OUT3        (PORT_ALT7_FUNC_MODE)
#define    PORT1_ADC0_SE1_CMP0_IN1        (PORT_ALT0_FUNC_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT1_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT1_FXIO_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT1_FTM1_QD_PHA        (PORT_ALT5_FUNC_MODE)
#define    PORT1_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT1_TRGMUX_OUT0        (PORT_ALT7_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_ADC1_SE0        (PORT_ALT0_FUNC_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT2_LPI2C0_SDA        (PORT_ALT3_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT2_FXIO_D4        (PORT_ALT5_FUNC_MODE)
#define    PORT2_LPUART0_RX        (PORT_ALT6_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_ADC1_SE1        (PORT_ALT0_FUNC_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT3_LPI2C0_SCL        (PORT_ALT3_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT3_FXIO_D5        (PORT_ALT5_FUNC_MODE)
#define    PORT3_LPUART0_TX        (PORT_ALT6_FUNC_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_CMP0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_EWM_OUT_b        (PORT_ALT5_FUNC_MODE)
#define    PORT4_JTAG_TMS_SWD_DIO        (PORT_ALT7_FUNC_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT5_RESET_b        (PORT_ALT7_FUNC_MODE)
#define    PORT6_ADC0_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_LPSPI1_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_FTM5_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT6_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT7_ADC0_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_FTM5_CH3        (PORT_ALT3_FUNC_MODE)
#define    PORT7_RTC_CLKIN        (PORT_ALT4_FUNC_MODE)
#define    PORT7_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FXIO_D6        (PORT_ALT4_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM3_FLT3        (PORT_ALT5_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT8_FTM4_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FXIO_D7        (PORT_ALT4_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM3_FLT2        (PORT_ALT5_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM1_FLT3        (PORT_ALT6_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT9_FTM4_FLT0        (PORT_ALT7_FUNC_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_FTM1_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT10_FXIO_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT10_JTAG_TDO        (PORT_ALT7_FUNC_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_FTM1_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT11_FXIO_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT11_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT11_SAI0_SYNC        (PORT_ALT6_FUNC_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_FTM1_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT12_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT12_SAI0_BCLK        (PORT_ALT7_FUNC_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_FTM1_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT13_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_FTM2_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT13_SAI0_D0        (PORT_ALT7_FUNC_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_EWM_IN        (PORT_ALT4_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_FTM1_FLT0        (PORT_ALT6_FUNC_MODE)
#define    PORT14_SAI0_D3        (PORT_ALT7_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_ADC1_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI0_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_LPSPI2_PCS3        (PORT_ALT4_FUNC_MODE)
#define    PORT15_FTM7_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_ADC1_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT16_LPSPI1_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_EWM_OUT_b        (PORT_ALT4_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT17_FTM5_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT18_GPIO        (PORT_GPIO_MODE)
#define    PORT18_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT18_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT18_LPSPI1_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT18_FTM6_CH0        (PORT_ALT5_FUNC_MODE)
#define    PORT19_GPIO        (PORT_GPIO_MODE)
#define    PORT19_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT19_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT19_LPSPI1_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT20_GPIO        (PORT_GPIO_MODE)
#define    PORT20_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT20_LPSPI1_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT21_GPIO        (PORT_GPIO_MODE)
#define    PORT21_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT21_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT21_LPSPI1_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT22_GPIO        (PORT_GPIO_MODE)
#define    PORT22_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT22_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT22_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT23_GPIO        (PORT_GPIO_MODE)
#define    PORT23_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT23_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT24_GPIO        (PORT_GPIO_MODE)
#define    PORT24_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT24_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_GPIO        (PORT_GPIO_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT25_FTM5_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_FTM5_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT26_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT27_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_FTM5_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT28_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPUART2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT29_LPSPI1_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_FTM5_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT30_LPSPI0_SOUT        (PORT_ALT4_FUNC_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT31_LPSPI0_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT32_ADC0_SE4_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_LPUART0_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT32_LPSPI0_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT32_LPTMR0_ALT3        (PORT_ALT4_FUNC_MODE)
#define    PORT32_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT32_FTM4_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT33_ADC0_SE5_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_LPUART0_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT33_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT33_TCLK0        (PORT_ALT4_FUNC_MODE)
#define    PORT33_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT33_FTM4_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT34_ADC0_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT34_LPSPI0_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT34_FTM1_QD_PHB        (PORT_ALT4_FUNC_MODE)
#define    PORT34_TRGMUX_IN3        (PORT_ALT6_FUNC_MODE)
#define    PORT35_ADC0_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_FTM1_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT35_LPSPI0_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT35_FTM1_QD_PHA        (PORT_ALT4_FUNC_MODE)
#define    PORT35_TRGMUX_IN2        (PORT_ALT6_FUNC_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT36_LPSPI0_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT36_MII_RMII_MDIO        (PORT_ALT5_FUNC_MODE)
#define    PORT36_TRGMUX_IN1        (PORT_ALT6_FUNC_MODE)
#define    PORT36_QSPI_B_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT37_LPSPI0_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT37_LPSPI0_PCS0        (PORT_ALT4_FUNC_MODE)
#define    PORT37_CLKOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT37_TRGMUX_IN0        (PORT_ALT6_FUNC_MODE)
#define    PORT37_MII_RMII_MDC        (PORT_ALT7_FUNC_MODE)
#define    PORT38_XTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LPI2C0_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT39_EXTAL        (PORT_ALT0_FUNC_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_LPI2C0_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_FTM3_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT40_SAI1_BCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_FTM3_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_LPI2C0_SCLS        (PORT_ALT3_FUNC_MODE)
#define    PORT41_SAI1_D0        (PORT_ALT4_FUNC_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_FTM3_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_LPI2C0_SDAS        (PORT_ALT3_FUNC_MODE)
#define    PORT42_SAI1_MCLK        (PORT_ALT4_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_FTM3_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT43_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_ADC1_SE7        (PORT_ALT0_FUNC_MODE)
#define    PORT44_GPIO        (PORT_GPIO_MODE)
#define    PORT44_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_FTM3_FLT2        (PORT_ALT3_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_CAN2_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT44_FTM6_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT45_ADC1_SE8_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_FTM3_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_CAN2_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT45_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_ADC1_SE9_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT46_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_ADC1_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT47_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_ADC1_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_GPIO        (PORT_GPIO_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_FTM0_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT48_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_GPIO        (PORT_GPIO_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_FTM0_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_LPSPI1_PCS3        (PORT_ALT3_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT49_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_ADC0_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_GPIO        (PORT_GPIO_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT50_LPSPI1_PCS1        (PORT_ALT4_FUNC_MODE)
#define    PORT51_GPIO        (PORT_GPIO_MODE)
#define    PORT51_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_ADC0_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_GPIO        (PORT_GPIO_MODE)
#define    PORT52_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_ADC0_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_GPIO        (PORT_GPIO_MODE)
#define    PORT53_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_ADC0_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_GPIO        (PORT_GPIO_MODE)
#define    PORT54_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT54_MII_CRS        (PORT_ALT3_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT54_LPUART1_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_ADC0_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_GPIO        (PORT_GPIO_MODE)
#define    PORT55_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT55_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT56_GPIO        (PORT_GPIO_MODE)
#define    PORT56_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_ADC0_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_GPIO        (PORT_GPIO_MODE)
#define    PORT57_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT57_LPSPI2_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT58_GPIO        (PORT_GPIO_MODE)
#define    PORT58_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_ADC0_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_GPIO        (PORT_GPIO_MODE)
#define    PORT59_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT59_LPSPI2_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_ADC0_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT60_LPSPI2_SIN        (PORT_ALT5_FUNC_MODE)
#define    PORT61_ADC0_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT61_LPSPI2_SCK        (PORT_ALT5_FUNC_MODE)
#define    PORT62_GPIO        (PORT_GPIO_MODE)
#define    PORT62_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT63_GPIO        (PORT_GPIO_MODE)
#define    PORT63_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT64_ADC0_SE8        (PORT_ALT0_FUNC_MODE)
#define    PORT64_GPIO        (PORT_GPIO_MODE)
#define    PORT64_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT64_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT64_FTM1_CH6        (PORT_ALT6_FUNC_MODE)
#define    PORT64_QSPI_B_RWDS        (PORT_ALT7_FUNC_MODE)
#define    PORT65_ADC0_SE9        (PORT_ALT0_FUNC_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_LPSPI2_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_1        (PORT_ALT4_FUNC_MODE)
#define    PORT65_MII_RMII_RXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT65_FTM1_CH7        (PORT_ALT6_FUNC_MODE)
#define    PORT65_QSPI_B_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT66_ADC0_SE10_CMP0_IN5        (PORT_ALT0_FUNC_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT66_CAN0_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT66_LPUART0_RX        (PORT_ALT4_FUNC_MODE)
#define    PORT66_MII_RMII_TXD_0        (PORT_ALT5_FUNC_MODE)
#define    PORT66_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT66_QSPI_A_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT67_ADC0_SE11_CMP0_IN4        (PORT_ALT0_FUNC_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT67_CAN0_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT67_LPUART0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT67_MII_TX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT67_QSPI_A_CS        (PORT_ALT6_FUNC_MODE)
#define    PORT67_QSPI_B_IO3        (PORT_ALT7_FUNC_MODE)
#define    PORT68_CMP0_IN2        (PORT_ALT0_FUNC_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_FTM1_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT68_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_EWM_IN        (PORT_ALT5_FUNC_MODE)
#define    PORT68_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT68_JTAG_TCLK_SWD_CLK        (PORT_ALT7_FUNC_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_RTC_CLKOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT69_LPI2C1_HREQ        (PORT_ALT4_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_FTM2_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT69_JTAG_TDI        (PORT_ALT7_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_ADC1_SE4        (PORT_ALT0_FUNC_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_CAN1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM3_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT70_FTM1_QD_PHB        (PORT_ALT6_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_ADC1_SE5        (PORT_ALT0_FUNC_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_CAN1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM3_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT71_FTM1_QD_PHA        (PORT_ALT6_FUNC_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_LPUART1_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FTM1_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_FTM5_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LPUART0_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_LPUART1_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT73_FTM1_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_FTM5_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT73_LPUART0_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT74_TRGMUX_IN11        (PORT_ALT6_FUNC_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_FTM4_CH2        (PORT_ALT3_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT75_TRGMUX_IN10        (PORT_ALT6_FUNC_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM3_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_FTM2_CH6        (PORT_ALT3_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT76_LPUART2_CTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM3_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_FTM2_CH7        (PORT_ALT3_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT77_LPUART2_RTS        (PORT_ALT4_FUNC_MODE)
#define    PORT78_ADC0_SE12        (PORT_ALT0_FUNC_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_FTM1_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_LPSPI2_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT78_MII_COL        (PORT_ALT4_FUNC_MODE)
#define    PORT78_TRGMUX_IN9        (PORT_ALT6_FUNC_MODE)
#define    PORT79_ADC0_SE13        (PORT_ALT0_FUNC_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_FTM1_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT79_MII_CRS        (PORT_ALT4_FUNC_MODE)
#define    PORT79_TRGMUX_IN8        (PORT_ALT6_FUNC_MODE)
#define    PORT79_QSPI_B_CS        (PORT_ALT7_FUNC_MODE)
#define    PORT80_ADC0_SE14        (PORT_ALT0_FUNC_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_FTM1_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT80_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT80_MII_RMII_RX_ER        (PORT_ALT5_FUNC_MODE)
#define    PORT80_QSPI_B_IO7        (PORT_ALT7_FUNC_MODE)
#define    PORT81_ADC0_SE15        (PORT_ALT0_FUNC_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT81_FTM1_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT81_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT81_MII_RMII_RX_DV        (PORT_ALT5_FUNC_MODE)
#define    PORT81_QSPI_B_IO6        (PORT_ALT7_FUNC_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT82_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT83_ADC0_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT83_LPSPI2_PCS1        (PORT_ALT5_FUNC_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT85_FTM7_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_FTM7_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT87_ADC0_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT87_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT91_ADC0_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT91_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT92_ADC0_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT92_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT93_ADC0_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT93_FTM5_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT94_ADC0_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FTM5_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT94_LPI2C1_SDAS        (PORT_ALT4_FUNC_MODE)
#define    PORT95_ADC0_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FTM5_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_FXIO_D1        (PORT_ALT3_FUNC_MODE)
#define    PORT95_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FTM0_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT96_LPSPI1_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_FTM2_CH0        (PORT_ALT4_FUNC_MODE)
#define    PORT96_ETM_TRACE_D0        (PORT_ALT5_FUNC_MODE)
#define    PORT96_FXIO_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT96_TRGMUX_OUT1        (PORT_ALT7_FUNC_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_FTM0_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT97_LPSPI1_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_FTM2_CH1        (PORT_ALT4_FUNC_MODE)
#define    PORT97_SAI0_MCLK        (PORT_ALT5_FUNC_MODE)
#define    PORT97_FXIO_D1        (PORT_ALT6_FUNC_MODE)
#define    PORT97_TRGMUX_OUT2        (PORT_ALT7_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_ADC1_SE2        (PORT_ALT0_FUNC_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FTM3_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT98_LPSPI1_SOUT        (PORT_ALT3_FUNC_MODE)
#define    PORT98_FXIO_D4        (PORT_ALT4_FUNC_MODE)
#define    PORT98_FXIO_D6        (PORT_ALT5_FUNC_MODE)
#define    PORT98_TRGMUX_IN5        (PORT_ALT6_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_ADC1_SE3        (PORT_ALT0_FUNC_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_FTM3_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT99_LPSPI1_PCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT99_FXIO_D5        (PORT_ALT4_FUNC_MODE)
#define    PORT99_FXIO_D7        (PORT_ALT5_FUNC_MODE)
#define    PORT99_TRGMUX_IN4        (PORT_ALT6_FUNC_MODE)
#define    PORT99_NMI_b        (PORT_ALT7_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_ADC1_SE6        (PORT_ALT0_FUNC_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT100_FTM3_FLT3        (PORT_ALT3_FUNC_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_FTM2_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT101_LPTMR0_ALT2        (PORT_ALT3_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT101_MII_TXD3        (PORT_ALT5_FUNC_MODE)
#define    PORT101_TRGMUX_IN7        (PORT_ALT6_FUNC_MODE)
#define    PORT101_QSPI_B_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT102_CMP0_IN7        (PORT_ALT0_FUNC_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_LPUART2_RX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT102_MII_TXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT102_QSPI_B_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT103_CMP0_IN6        (PORT_ALT0_FUNC_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_LPUART2_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT103_MII_RMII_TXD_1        (PORT_ALT5_FUNC_MODE)
#define    PORT103_ETM_TRACE_D0        (PORT_ALT6_FUNC_MODE)
#define    PORT103_QSPI_A_IO1        (PORT_ALT7_FUNC_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_LPI2C1_SDA        (PORT_ALT2_FUNC_MODE)
#define    PORT104_MII_RXD3        (PORT_ALT3_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FTM2_FLT2        (PORT_ALT4_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FXIO_D1        (PORT_ALT5_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_FTM1_CH4        (PORT_ALT6_FUNC_MODE)
#define    PORT104_QSPI_B_IO5        (PORT_ALT7_FUNC_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_LPI2C1_SCL        (PORT_ALT2_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FXIO_D0        (PORT_ALT3_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_FTM2_FLT3        (PORT_ALT4_FUNC_MODE)
#define    PORT105_MII_RXD2        (PORT_ALT5_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_FTM1_CH5        (PORT_ALT6_FUNC_MODE)
#define    PORT105_QSPI_B_IO4        (PORT_ALT7_FUNC_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT106_ETM_TRACE_D3        (PORT_ALT4_FUNC_MODE)
#define    PORT106_MII_RX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT106_QSPI_A_SCK        (PORT_ALT7_FUNC_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT107_ETM_TRACE_D2        (PORT_ALT4_FUNC_MODE)
#define    PORT107_MII_RMII_TX_CLK        (PORT_ALT5_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_LPUART2_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT107_QSPI_A_IO0        (PORT_ALT7_FUNC_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_FTM2_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT108_LPI2C1_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT108_ETM_TRACE_D1        (PORT_ALT4_FUNC_MODE)
#define    PORT108_MII_RMII_TX_EN        (PORT_ALT5_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_LPUART2_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT108_QSPI_A_IO2        (PORT_ALT7_FUNC_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_FTM2_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_LPUART1_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT109_ENET_TMR1        (PORT_ALT5_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT109_RTC_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_FTM2_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_LPUART1_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT110_ENET_TMR0        (PORT_ALT5_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT110_CLKOUT        (PORT_ALT7_FUNC_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_FTM0_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT111_ETM_TRACE_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT111_LPSPI0_SCK        (PORT_ALT4_FUNC_MODE)
#define    PORT111_ENET_TMR2        (PORT_ALT5_FUNC_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_FTM0_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT112_ETM_TRACE_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT112_LPSPI0_SIN        (PORT_ALT4_FUNC_MODE)
#define    PORT112_CMP0_RRT        (PORT_ALT5_FUNC_MODE)
#define    PORT112_ETM_TRACE_CLKOUT        (PORT_ALT6_FUNC_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_FTM0_FLT2        (PORT_ALT2_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_LPUART2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT113_FTM5_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_ADC1_SE16        (PORT_ALT0_FUNC_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FTM5_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_FXIO_D2        (PORT_ALT3_FUNC_MODE)
#define    PORT114_LPI2C1_SCLS        (PORT_ALT4_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_ADC1_SE17        (PORT_ALT0_FUNC_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_FTM6_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_FXIO_D3        (PORT_ALT3_FUNC_MODE)
#define    PORT115_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_FTM6_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_FTM6_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_ADC1_SE18        (PORT_ALT0_FUNC_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_FTM6_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_ADC1_SE19        (PORT_ALT0_FUNC_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_FTM6_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_ADC1_SE20        (PORT_ALT0_FUNC_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_FTM6_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_FTM6_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_FTM6_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT122_FXIO_D7        (PORT_ALT3_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_ADC1_SE21        (PORT_ALT0_FUNC_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_FTM7_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_ADC1_SE22        (PORT_ALT0_FUNC_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_FTM7_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_ADC1_SE23        (PORT_ALT0_FUNC_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_FTM7_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT126_ADC1_SE24        (PORT_ALT0_FUNC_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_FTM7_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT126_FTM6_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_FTM7_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT127_FXIO_D6        (PORT_ALT3_FUNC_MODE)
#define    PORT127_FTM6_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_LPSPI0_SCK        (PORT_ALT2_FUNC_MODE)
#define    PORT128_TCLK1        (PORT_ALT3_FUNC_MODE)
#define    PORT128_LPI2C1_SDA        (PORT_ALT4_FUNC_MODE)
#define    PORT128_LPSPI1_SOUT        (PORT_ALT5_FUNC_MODE)
#define    PORT128_FTM1_FLT2        (PORT_ALT6_FUNC_MODE)
#define    PORT128_SAI0_D2        (PORT_ALT7_FUNC_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_LPSPI0_SIN        (PORT_ALT2_FUNC_MODE)
#define    PORT129_LPI2C0_HREQ        (PORT_ALT3_FUNC_MODE)
#define    PORT129_LPI2C1_SCL        (PORT_ALT4_FUNC_MODE)
#define    PORT129_LPSPI1_PCS0        (PORT_ALT5_FUNC_MODE)
#define    PORT129_FTM1_FLT1        (PORT_ALT6_FUNC_MODE)
#define    PORT129_SAI0_D1        (PORT_ALT7_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_ADC1_SE10        (PORT_ALT0_FUNC_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_LPSPI0_SOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT130_LPTMR0_ALT3        (PORT_ALT3_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_FTM3_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT130_LPUART1_CTS        (PORT_ALT6_FUNC_MODE)
#define    PORT130_SAI1_SYNC        (PORT_ALT7_FUNC_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_FTM0_FLT0        (PORT_ALT2_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_LPUART2_RTS        (PORT_ALT3_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT131_TRGMUX_IN6        (PORT_ALT6_FUNC_MODE)
#define    PORT131_CMP0_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_ETM_TRACE_D1        (PORT_ALT2_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_QD_PHB        (PORT_ALT3_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_FTM2_CH2        (PORT_ALT4_FUNC_MODE)
#define    PORT132_CAN0_RX        (PORT_ALT5_FUNC_MODE)
#define    PORT132_FXIO_D6        (PORT_ALT6_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT132_EWM_OUT_b        (PORT_ALT7_FUNC_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_TCLK2        (PORT_ALT2_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_QD_PHA        (PORT_ALT3_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_FTM2_CH3        (PORT_ALT4_FUNC_MODE)
#define    PORT133_CAN0_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT133_FXIO_D7        (PORT_ALT6_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT133_EWM_IN        (PORT_ALT7_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_ADC1_SE11        (PORT_ALT0_FUNC_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_LPSPI0_PCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT134_FTM7_FLT1        (PORT_ALT3_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_FTM3_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT134_LPUART1_RTS        (PORT_ALT6_FUNC_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT135_FTM3_FLT0        (PORT_ALT3_FUNC_MODE)
#define    PORT136_CMP0_IN3        (PORT_ALT0_FUNC_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_FTM0_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT136_MII_RMII_MDC        (PORT_ALT5_FUNC_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_FTM0_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_LPUART2_CTS        (PORT_ALT3_FUNC_MODE)
#define    PORT137_ENET_TMR3        (PORT_ALT5_FUNC_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_CLKOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_LPSPI2_PCS1        (PORT_ALT3_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FTM2_CH4        (PORT_ALT4_FUNC_MODE)
#define    PORT138_FXIO_D4        (PORT_ALT6_FUNC_MODE)
#define    PORT138_TRGMUX_OUT4        (PORT_ALT7_FUNC_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPSPI2_PCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT139_LPTMR0_ALT1        (PORT_ALT3_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FTM2_CH5        (PORT_ALT4_FUNC_MODE)
#define    PORT139_FXIO_D5        (PORT_ALT6_FUNC_MODE)
#define    PORT139_TRGMUX_OUT5        (PORT_ALT7_FUNC_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_FTM0_FLT3        (PORT_ALT2_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_LPUART2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT140_FTM5_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_LPSPI2_PCS2        (PORT_ALT3_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT141_FTM2_FLT0        (PORT_ALT4_FUNC_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM0_FLT1        (PORT_ALT2_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT142_FTM2_FLT1        (PORT_ALT4_FUNC_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPUART1_CTS        (PORT_ALT2_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_LPSPI2_SCK        (PORT_ALT3_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM2_CH6        (PORT_ALT4_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FTM4_FLT1        (PORT_ALT5_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_FXIO_D2        (PORT_ALT6_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT143_TRGMUX_OUT6        (PORT_ALT7_FUNC_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPUART1_RTS        (PORT_ALT2_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_LPSPI2_SIN        (PORT_ALT3_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM2_CH7        (PORT_ALT4_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FTM4_FLT0        (PORT_ALT5_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_FXIO_D3        (PORT_ALT6_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT144_TRGMUX_OUT7        (PORT_ALT7_FUNC_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_FTM7_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT145_FXIO_D5        (PORT_ALT3_FUNC_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_FTM7_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT146_FXIO_D4        (PORT_ALT3_FUNC_MODE)
#define    PORT147_ADC1_SE25        (PORT_ALT0_FUNC_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_FTM7_CH7        (PORT_ALT2_FUNC_MODE)
#define    PORT148_ADC1_SE26        (PORT_ALT0_FUNC_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT148_FTM4_CH0        (PORT_ALT2_FUNC_MODE)
#define    PORT149_ADC1_SE27        (PORT_ALT0_FUNC_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT149_FTM4_CH1        (PORT_ALT2_FUNC_MODE)
#define    PORT150_ADC1_SE28        (PORT_ALT0_FUNC_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT150_FTM4_CH2        (PORT_ALT2_FUNC_MODE)
#define    PORT151_ADC1_SE29        (PORT_ALT0_FUNC_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT151_FTM4_CH3        (PORT_ALT2_FUNC_MODE)
#define    PORT152_ADC1_SE30        (PORT_ALT0_FUNC_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_FTM4_CH4        (PORT_ALT2_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT152_CAN2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_ADC1_SE31        (PORT_ALT0_FUNC_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_FTM4_CH5        (PORT_ALT2_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT153_CAN2_RX        (PORT_ALT3_FUNC_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_FTM4_CH6        (PORT_ALT2_FUNC_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_FTM4_CH7        (PORT_ALT2_FUNC_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_"!]

[!ENDVAR!]




[!VAR "CHECK_1"!]

/*  Mode PORT_ALT0_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_ADC0_SE0_CMP0_IN0 |
PORT1_ADC0_SE1_CMP0_IN1 |
PORT7_ADC0_SE3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(7)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_ADC0_SE4_ADC1_SE14 |
PORT33_ADC0_SE5_ADC1_SE15 |
PORT34_ADC0_SE6 |
PORT35_ADC0_SE7 |
PORT38_XTAL |
PORT39_EXTAL |
PORT45_ADC1_SE8_ADC0_SE8 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(13)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT65_ADC0_SE9 |
PORT66_ADC0_SE10_CMP0_IN5 |
PORT67_ADC0_SE11_CMP0_IN4 |
PORT68_CMP0_IN2 |
PORT78_ADC0_SE12 |
PORT79_ADC0_SE13 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_ADC0_SE14 */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT136_CMP0_IN3 */
  (uint16)( SHL_PAD_U16(8)
          )
}
,
/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT7_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT45_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(13)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT101_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 : PORT132_GPIO |
PORT133_GPIO |
PORT136_GPIO |
PORT137_GPIO */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT1_FTM1_CH1 |
PORT7_FTM0_FLT2 |
PORT10_FTM1_CH4 |
PORT11_FTM1_CH5 |
PORT12_FTM1_CH6 |
PORT13_FTM1_CH7 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_LPUART0_RX |
PORT33_LPUART0_TX |
PORT34_FTM1_CH0 |
PORT35_FTM1_CH1 |
PORT36_FTM0_CH4 |
PORT37_FTM0_CH5 |
PORT38_LPI2C0_SDA |
PORT39_LPI2C0_SCL |
PORT45_FTM0_CH1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(13)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT65_FTM0_CH1 |
PORT66_FTM0_CH2 |
PORT67_FTM0_CH3 |
PORT68_FTM1_CH0 |
PORT70_LPUART1_RX |
PORT71_LPUART1_TX |
PORT72_LPUART1_RX |
PORT73_LPUART1_TX |
PORT78_FTM1_CH2 |
PORT79_FTM1_CH3 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_FTM1_FLT2 */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads  96 ... 111 : PORT96_FTM0_CH2 |
PORT97_FTM0_CH3 |
PORT111_FTM0_CH0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_FTM0_CH1 */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 : PORT133_TCLK2 |
PORT136_FTM0_CH6 |
PORT137_FTM0_CH7 */
  (uint16)( SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPI2C0_SCLS |
PORT1_LPI2C0_SDAS |
PORT2_LPI2C0_SDA |
PORT3_LPI2C0_SCL |
PORT5_TCLK1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_LPSPI0_PCS0 |
PORT33_LPSPI0_SOUT |
PORT34_LPSPI0_SCK |
PORT35_LPSPI0_SIN |
PORT36_LPSPI0_SOUT |
PORT37_LPSPI0_PCS1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT66_CAN0_RX |
PORT67_CAN0_TX |
PORT68_RTC_CLKOUT |
PORT69_RTC_CLKOUT |
PORT72_FTM1_FLT0 |
PORT73_FTM1_FLT1 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT96_LPSPI1_SCK |
PORT97_LPSPI1_SIN |
PORT98_LPSPI1_SOUT |
PORT99_LPSPI1_PCS0 |
PORT101_LPTMR0_ALT2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FXIO_D2 |
PORT1_FXIO_D3 |
PORT4_CMP0_OUT |
PORT7_RTC_CLKIN |
PORT10_FXIO_D0 |
PORT11_FXIO_D1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_LPTMR0_ALT3 |
PORT33_TCLK0 |
PORT34_FTM1_QD_PHB |
PORT35_FTM1_QD_PHA |
PORT37_LPSPI0_PCS0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT66_LPUART0_RX |
PORT67_LPUART0_TX */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(3)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT98_FXIO_D4 |
PORT99_FXIO_D5 |
PORT111_LPSPI0_SCK */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_LPSPI0_SIN */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT1_FTM1_QD_PHA |
PORT2_FXIO_D4 |
PORT3_FXIO_D5 |
PORT11_CMP0_RRT */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(11)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_CAN0_RX |
PORT33_CAN0_TX |
PORT37_CLKOUT */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT98_FXIO_D6 |
PORT99_FXIO_D7 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(3)
          ),
/* Pads 112 ... 127 : PORT112_CMP0_RRT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 : PORT132_CAN0_RX |
PORT133_CAN0_TX */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          )
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPUART0_CTS |
PORT1_LPUART0_RTS |
PORT2_LPUART0_RX |
PORT3_LPUART0_TX |
PORT7_LPUART1_RTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(7)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT34_TRGMUX_IN3 |
PORT35_TRGMUX_IN2 |
PORT36_TRGMUX_IN1 |
PORT37_TRGMUX_IN0 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT65_FTM1_CH7 |
PORT68_FTM1_QD_PHB |
PORT70_FTM1_QD_PHB |
PORT71_FTM1_QD_PHA |
PORT72_LPUART0_CTS |
PORT73_LPUART0_RTS |
PORT78_TRGMUX_IN9 |
PORT79_TRGMUX_IN8 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT96_FXIO_D0 |
PORT97_FXIO_D1 |
PORT98_TRGMUX_IN5 |
PORT99_TRGMUX_IN4 |
PORT101_TRGMUX_IN7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT132_FXIO_D6 |
PORT133_FXIO_D7 */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_TRGMUX_OUT3 |
PORT1_TRGMUX_OUT0 |
PORT4_JTAG_TMS_SWD_DIO |
PORT5_RESET_b |
PORT10_JTAG_TDO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(10)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT68_JTAG_TCLK_SWD_CLK |
PORT69_JTAG_TDI */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT96_TRGMUX_OUT1 |
PORT97_TRGMUX_OUT2 |
PORT99_NMI_b */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000
}

[!ENDVAR!]




[!VAR "CHECK_2"!]

/*  Mode PORT_ALT0_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_ADC0_SE0_CMP0_IN0 |
PORT1_ADC0_SE1_CMP0_IN1 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT6_ADC0_SE2 |
PORT7_ADC0_SE3 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          ),
/* Pads  32 ...  47 : PORT32_ADC0_SE4_ADC1_SE14 |
PORT33_ADC0_SE5_ADC1_SE15 |
PORT34_ADC0_SE6 |
PORT35_ADC0_SE7 |
PORT38_XTAL |
PORT39_EXTAL |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT45_ADC1_SE8_ADC0_SE8 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT50_ADC0_SE16 |
PORT50_ADC0_SE16 |
PORT52_ADC0_SE17 |
PORT52_ADC0_SE17 |
PORT53_ADC0_SE18 |
PORT53_ADC0_SE18 |
PORT54_ADC0_SE19 |
PORT54_ADC0_SE19 |
PORT55_ADC0_SE20 |
PORT55_ADC0_SE20 |
PORT57_ADC0_SE21 |
PORT57_ADC0_SE21 |
PORT59_ADC0_SE22 |
PORT59_ADC0_SE22 |
PORT60_ADC0_SE23 |
PORT60_ADC0_SE23 |
PORT61_ADC0_SE24 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_ADC0_SE8 |
PORT65_ADC0_SE9 |
PORT66_ADC0_SE10_CMP0_IN5 |
PORT67_ADC0_SE11_CMP0_IN4 |
PORT68_CMP0_IN2 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT78_ADC0_SE12 |
PORT79_ADC0_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_ADC0_SE14 |
PORT81_ADC0_SE15 |
PORT83_ADC0_SE25 |
PORT87_ADC0_SE26 |
PORT91_ADC0_SE27 |
PORT92_ADC0_SE28 |
PORT93_ADC0_SE29 |
PORT94_ADC0_SE30 |
PORT95_ADC0_SE31 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT102_CMP0_IN7 |
PORT103_CMP0_IN6 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7)
          ),
/* Pads 112 ... 127 : PORT114_ADC1_SE16 |
PORT114_ADC1_SE16 |
PORT115_ADC1_SE17 |
PORT115_ADC1_SE17 |
PORT118_ADC1_SE18 |
PORT118_ADC1_SE18 |
PORT119_ADC1_SE19 |
PORT119_ADC1_SE19 |
PORT120_ADC1_SE20 |
PORT120_ADC1_SE20 |
PORT123_ADC1_SE21 |
PORT123_ADC1_SE21 |
PORT124_ADC1_SE22 |
PORT124_ADC1_SE22 |
PORT125_ADC1_SE23 |
PORT125_ADC1_SE23 |
PORT126_ADC1_SE24 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT136_CMP0_IN3 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(8)
          )
}
,
/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT147_ADC1_SE25 |
PORT148_ADC1_SE26 |
PORT149_ADC1_SE27 |
PORT150_ADC1_SE28 |
PORT151_ADC1_SE29 |
PORT152_ADC1_SE30 |
PORT153_ADC1_SE31 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT20_GPIO |
PORT21_GPIO |
PORT22_GPIO |
PORT23_GPIO |
PORT24_GPIO |
PORT25_GPIO |
PORT25_GPIO |
PORT26_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT30_GPIO |
PORT31_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT50_GPIO |
PORT50_GPIO |
PORT51_GPIO |
PORT52_GPIO |
PORT52_GPIO |
PORT53_GPIO |
PORT53_GPIO |
PORT54_GPIO |
PORT54_GPIO |
PORT55_GPIO |
PORT55_GPIO |
PORT56_GPIO |
PORT57_GPIO |
PORT57_GPIO |
PORT58_GPIO |
PORT59_GPIO |
PORT59_GPIO |
PORT60_GPIO |
PORT60_GPIO |
PORT61_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT94_GPIO |
PORT95_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT137_GPIO |
PORT138_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT1_FTM1_CH1 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT6_FTM0_FLT1 |
PORT7_FTM0_FLT2 |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT10_FTM1_CH4 |
PORT11_FTM1_CH5 |
PORT12_FTM1_CH6 |
PORT13_FTM1_CH7 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT148_GPIO |
PORT149_GPIO |
PORT149_GPIO |
PORT150_GPIO |
PORT150_GPIO |
PORT151_GPIO |
PORT151_GPIO |
PORT152_GPIO |
PORT152_GPIO |
PORT153_GPIO |
PORT153_GPIO |
PORT154_GPIO |
PORT155_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          ),
/* Pads  16 ...  31 : PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT18_FTM4_CH0 |
PORT19_FTM4_CH1 |
PORT20_FTM4_CH2 |
PORT21_FTM4_CH3 |
PORT22_FTM4_CH4 |
PORT23_FTM4_CH6 |
PORT24_FTM4_CH7 |
PORT25_FTM5_CH0 |
PORT25_FTM5_CH0 |
PORT26_FTM5_CH1 |
PORT26_FTM5_CH1 |
PORT27_FTM5_CH2 |
PORT27_FTM5_CH2 |
PORT28_FTM5_CH3 |
PORT28_FTM5_CH3 |
PORT29_FTM5_CH4 |
PORT29_FTM5_CH4 |
PORT30_FTM5_CH5 |
PORT30_FTM5_CH5 |
PORT31_FTM5_CH6 |
PORT31_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPUART0_RX |
PORT33_LPUART0_TX |
PORT34_FTM1_CH0 |
PORT35_FTM1_CH1 |
PORT36_FTM0_CH4 |
PORT37_FTM0_CH5 |
PORT38_LPI2C0_SDA |
PORT39_LPI2C0_SCL |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT44_FTM0_CH0 |
PORT45_FTM0_CH1 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT50_FTM5_CH7 |
PORT50_FTM5_CH7 |
PORT51_FTM5_CH7 |
PORT52_FTM6_CH0 |
PORT53_FTM6_CH1 |
PORT54_FTM6_CH2 |
PORT55_FTM6_CH3 |
PORT56_FTM6_CH4 |
PORT57_FTM6_CH5 |
PORT58_FTM6_CH6 |
PORT59_FTM6_CH7 |
PORT60_FTM7_CH0 |
PORT61_FTM7_CH1 |
PORT62_FTM7_CH2 |
PORT63_FTM7_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_FTM0_CH0 |
PORT65_FTM0_CH1 |
PORT66_FTM0_CH2 |
PORT67_FTM0_CH3 |
PORT68_FTM1_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT70_LPUART1_RX |
PORT71_LPUART1_TX |
PORT72_LPUART1_RX |
PORT73_LPUART1_TX |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT78_FTM1_CH2 |
PORT79_FTM1_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_FTM1_FLT2 |
PORT81_FTM1_FLT3 |
PORT82_FTM7_CH4 |
PORT83_FTM7_CH5 |
PORT84_FTM7_CH6 |
PORT85_FTM7_CH7 |
PORT86_FTM7_FLT1 |
PORT87_LPSPI0_SCK |
PORT87_LPSPI0_SCK |
PORT88_FTM4_CH0 |
PORT89_FTM4_CH1 |
PORT90_FTM4_CH3 |
PORT91_FTM4_CH4 |
PORT91_FTM4_CH4 |
PORT92_FTM4_CH7 |
PORT92_FTM4_CH7 |
PORT93_FTM5_CH2 |
PORT93_FTM5_CH2 |
PORT94_FTM5_CH4 |
PORT94_FTM5_CH4 |
PORT95_FTM5_CH6 |
PORT95_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM0_CH2 |
PORT97_FTM0_CH3 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT100_FTM0_FLT3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT104_LPI2C1_SDA |
PORT105_LPI2C1_SCL |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT111_FTM0_CH0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_FTM0_CH1 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT114_FTM5_CH7 |
PORT114_FTM5_CH7 |
PORT115_FTM6_CH0 |
PORT116_FTM6_CH1 |
PORT117_FTM6_CH2 |
PORT118_FTM6_CH3 |
PORT119_FTM6_CH4 |
PORT120_FTM6_CH5 |
PORT121_FTM6_CH6 |
PORT122_FTM6_CH7 |
PORT123_FTM7_CH0 |
PORT124_FTM7_CH1 |
PORT125_FTM7_CH2 |
PORT126_FTM7_CH3 |
PORT127_FTM7_CH4 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI0_SCK |
PORT129_LPSPI0_SIN |
PORT130_LPSPI0_SOUT |
PORT131_FTM0_FLT0 |
PORT132_ETM_TRACE_D1 |
PORT133_TCLK2 |
PORT134_LPSPI0_PCS2 |
PORT135_FTM0_CH7 |
PORT136_FTM0_CH6 |
PORT137_FTM0_CH7 |
PORT138_CLKOUT |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT141_FTM4_CH5 |
PORT141_FTM4_CH5 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPI2C0_SCLS |
PORT1_LPI2C0_SDAS |
PORT2_LPI2C0_SDA |
PORT3_LPI2C0_SCL |
PORT5_TCLK1 |
PORT6_LPSPI1_PCS1 |
PORT7_FTM5_CH3 |
PORT7_FTM5_CH3 |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT145_FTM7_CH5 |
PORT146_FTM7_CH6 |
PORT147_FTM7_CH7 |
PORT148_FTM4_CH0 |
PORT148_FTM4_CH0 |
PORT149_FTM4_CH1 |
PORT149_FTM4_CH1 |
PORT150_FTM4_CH2 |
PORT150_FTM4_CH2 |
PORT151_FTM4_CH3 |
PORT151_FTM4_CH3 |
PORT152_FTM4_CH4 |
PORT152_FTM4_CH4 |
PORT153_FTM4_CH5 |
PORT153_FTM4_CH5 |
PORT154_FTM4_CH6 |
PORT155_FTM4_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          ),
/* Pads  16 ...  31 : PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT18_LPUART1_TX |
PORT19_LPUART1_RX |
PORT21_FXIO_D0 |
PORT22_FXIO_D1 |
PORT23_FXIO_D2 |
PORT24_FXIO_D3 |
PORT26_LPSPI1_PCS0 |
PORT26_LPSPI1_PCS0 |
PORT27_LPSPI1_SOUT |
PORT27_LPSPI1_SOUT |
PORT28_LPSPI1_SCK |
PORT28_LPSPI1_SCK |
PORT30_LPUART2_RX |
PORT30_LPUART2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads  32 ...  47 : PORT32_LPSPI0_PCS0 |
PORT33_LPSPI0_SOUT |
PORT34_LPSPI0_SCK |
PORT35_LPSPI0_SIN |
PORT36_LPSPI0_SOUT |
PORT37_LPSPI0_PCS1 |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT54_MII_CRS |
PORT55_LPUART1_RX |
PORT55_LPUART1_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT66_CAN0_RX |
PORT67_CAN0_TX |
PORT68_RTC_CLKOUT |
PORT69_RTC_CLKOUT |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT72_FTM1_FLT0 |
PORT73_FTM1_FLT1 |
PORT75_FTM4_CH2 |
PORT75_FTM4_CH2 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT94_FXIO_D0 |
PORT94_FXIO_D0 |
PORT95_FXIO_D1 |
PORT95_FXIO_D1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_LPSPI1_SCK |
PORT97_LPSPI1_SIN |
PORT98_LPSPI1_SOUT |
PORT99_LPSPI1_PCS0 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT101_LPTMR0_ALT2 |
PORT104_MII_RXD3 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT108_LPI2C1_HREQ |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT111_ETM_TRACE_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_D2 |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT114_FXIO_D2 |
PORT114_FXIO_D2 |
PORT115_FXIO_D3 |
PORT115_FXIO_D3 |
PORT122_FXIO_D7 |
PORT126_FTM6_FLT1 |
PORT127_FXIO_D6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_TCLK1 |
PORT129_LPI2C0_HREQ |
PORT130_LPTMR0_ALT3 |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT134_FTM7_FLT1 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT139_LPTMR0_ALT1 |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FXIO_D2 |
PORT1_FXIO_D3 |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT4_CMP0_OUT |
PORT6_FTM5_CH5 |
PORT6_FTM5_CH5 |
PORT7_RTC_CLKIN |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT10_FXIO_D0 |
PORT11_FXIO_D1 |
PORT12_LPI2C1_SDAS |
PORT13_LPI2C1_SCLS |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 |
PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT145_FXIO_D5 |
PORT146_FXIO_D4 |
PORT152_CAN2_TX |
PORT152_CAN2_TX |
PORT153_CAN2_RX |
PORT153_CAN2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9)
          ),
/* Pads  16 ...  31 : PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT18_LPSPI1_SOUT |
PORT19_LPSPI1_SCK |
PORT20_LPSPI1_SIN |
PORT21_LPSPI1_PCS0 |
PORT22_LPSPI1_PCS1 |
PORT26_LPSPI0_PCS0 |
PORT26_LPSPI0_PCS0 |
PORT27_LPUART0_TX |
PORT27_LPUART0_TX |
PORT28_LPUART0_RX |
PORT28_LPUART0_RX |
PORT29_LPUART2_TX |
PORT29_LPUART2_TX |
PORT30_LPSPI0_SOUT |
PORT30_LPSPI0_SOUT |
PORT31_LPSPI0_PCS1 |
PORT31_LPSPI0_PCS1 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPTMR0_ALT3 |
PORT33_TCLK0 |
PORT34_FTM1_QD_PHB |
PORT35_FTM1_QD_PHA |
PORT37_LPSPI0_PCS0 |
PORT40_SAI1_BCLK |
PORT41_SAI1_D0 |
PORT42_SAI1_MCLK |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT45_CAN2_TX |
PORT45_CAN2_TX |
PORT45_CAN2_TX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT49_FTM5_FLT1 |
PORT49_FTM5_FLT1 |
PORT50_LPSPI1_PCS1 |
PORT50_LPSPI1_PCS1 |
PORT55_MII_COL */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_1 |
PORT65_MII_RMII_RXD_1 |
PORT66_LPUART0_RX |
PORT67_LPUART0_TX |
PORT69_LPI2C1_HREQ |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT72_FTM5_CH1 |
PORT72_FTM5_CH1 |
PORT73_FTM5_CH0 |
PORT73_FTM5_CH0 |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT78_MII_COL |
PORT79_MII_CRS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_LPI2C1_SDAS |
PORT81_LPI2C1_SCLS |
PORT85_FTM7_FLT0 |
PORT94_LPI2C1_SDAS |
PORT95_LPI2C1_SDA */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT98_FXIO_D4 |
PORT99_FXIO_D5 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT106_ETM_TRACE_D3 |
PORT107_ETM_TRACE_D2 |
PORT108_ETM_TRACE_D1 |
PORT111_LPSPI0_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_LPSPI0_SIN |
PORT113_FTM5_FLT1 |
PORT113_FTM5_FLT1 |
PORT114_LPI2C1_SCLS |
PORT115_LPI2C1_SCL */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3)
          ),
/* Pads 128 ... 143 : PORT128_LPI2C1_SDA |
PORT129_LPI2C1_SCL |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT140_FTM5_FLT0 |
PORT140_FTM5_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT1_FTM1_QD_PHA |
PORT2_FXIO_D4 |
PORT3_FXIO_D5 |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT11_CMP0_RRT |
PORT15_FTM7_FLT0 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          ),
/* Pads  16 ...  31 : PORT17_FTM5_FLT0 |
PORT17_FTM5_FLT0 |
PORT18_FTM6_CH0 |
PORT27_CAN0_TX |
PORT27_CAN0_TX |
PORT28_CAN0_RX |
PORT28_CAN0_RX |
PORT29_LPSPI1_SIN |
PORT29_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  32 ...  47 : PORT32_CAN0_RX |
PORT33_CAN0_TX |
PORT36_MII_RMII_MDIO |
PORT37_CLKOUT |
PORT44_FTM6_FLT1 |
PORT45_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT54_LPUART1_TX |
PORT54_LPUART1_TX |
PORT57_LPSPI2_PCS0 |
PORT57_LPSPI2_PCS0 |
PORT59_LPSPI2_SOUT |
PORT59_LPSPI2_SOUT |
PORT60_LPSPI2_SIN |
PORT60_LPSPI2_SIN |
PORT61_LPSPI2_SCK |
PORT61_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_0 |
PORT65_MII_RMII_RXD_0 |
PORT66_MII_RMII_TXD_0 |
PORT67_MII_TX_ER |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4)
          ),
/* Pads  80 ...  95 : PORT80_MII_RMII_RX_ER |
PORT81_MII_RMII_RX_DV |
PORT83_LPSPI2_PCS1 |
PORT83_LPSPI2_PCS1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3)
          ),
/* Pads  96 ... 111 : PORT96_ETM_TRACE_D0 |
PORT97_SAI0_MCLK |
PORT98_FXIO_D6 |
PORT99_FXIO_D7 |
PORT101_MII_TXD3 |
PORT102_MII_TXD2 |
PORT103_MII_RMII_TXD_1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT105_MII_RXD2 |
PORT106_MII_RX_CLK |
PORT107_MII_RMII_TX_CLK |
PORT108_MII_RMII_TX_EN |
PORT109_ENET_TMR1 |
PORT110_ENET_TMR0 |
PORT111_ENET_TMR2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_CMP0_RRT |
PORT127_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI1_SOUT |
PORT129_LPSPI1_PCS0 |
PORT132_CAN0_RX |
PORT133_CAN0_TX |
PORT136_MII_RMII_MDC |
PORT137_ENET_TMR3 |
PORT143_FTM4_FLT1 |
PORT143_FTM4_FLT1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPUART0_CTS |
PORT1_LPUART0_RTS |
PORT2_LPUART0_RX |
PORT3_LPUART0_TX |
PORT6_LPUART1_CTS |
PORT7_LPUART1_RTS |
PORT8_FTM4_FLT1 |
PORT8_FTM4_FLT1 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT11_SAI0_SYNC |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT144_FTM4_FLT0 |
PORT144_FTM4_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_FTM4_CH6 |
PORT32_FTM4_CH6 |
PORT33_FTM4_CH5 |
PORT33_FTM4_CH5 |
PORT34_TRGMUX_IN3 |
PORT35_TRGMUX_IN2 |
PORT36_TRGMUX_IN1 |
PORT37_TRGMUX_IN0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_FTM1_CH6 |
PORT65_FTM1_CH7 |
PORT66_ETM_TRACE_CLKOUT |
PORT67_QSPI_A_CS |
PORT68_FTM1_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT70_FTM1_QD_PHB |
PORT71_FTM1_QD_PHA |
PORT72_LPUART0_CTS |
PORT73_LPUART0_RTS |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT78_TRGMUX_IN9 |
PORT79_TRGMUX_IN8 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT96_FXIO_D0 |
PORT97_FXIO_D1 |
PORT98_TRGMUX_IN5 |
PORT99_TRGMUX_IN4 |
PORT101_TRGMUX_IN7 |
PORT103_ETM_TRACE_D0 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT106_CLKOUT |
PORT106_CLKOUT |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_CLKOUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 : PORT128_FTM1_FLT2 |
PORT129_FTM1_FLT1 |
PORT130_LPUART1_CTS |
PORT131_TRGMUX_IN6 |
PORT132_FXIO_D6 |
PORT133_FXIO_D7 |
PORT134_LPUART1_RTS |
PORT138_FXIO_D4 |
PORT139_FXIO_D5 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_TRGMUX_OUT3 |
PORT1_TRGMUX_OUT0 |
PORT4_JTAG_TMS_SWD_DIO |
PORT5_RESET_b |
PORT9_FTM4_FLT0 |
PORT9_FTM4_FLT0 |
PORT10_JTAG_TDO |
PORT12_SAI0_BCLK |
PORT13_SAI0_D0 |
PORT14_SAI0_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT36_QSPI_B_IO0 |
PORT37_MII_RMII_MDC */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_QSPI_B_RWDS |
PORT65_QSPI_B_SCK |
PORT66_QSPI_A_IO3 |
PORT67_QSPI_B_IO3 |
PORT68_JTAG_TCLK_SWD_CLK |
PORT69_JTAG_TDI |
PORT79_QSPI_B_CS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_QSPI_B_IO7 |
PORT81_QSPI_B_IO6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1)
          ),
/* Pads  96 ... 111 : PORT96_TRGMUX_OUT1 |
PORT97_TRGMUX_OUT2 |
PORT99_NMI_b |
PORT101_QSPI_B_IO2 |
PORT102_QSPI_B_IO1 |
PORT103_QSPI_A_IO1 |
PORT104_QSPI_B_IO5 |
PORT105_QSPI_B_IO4 |
PORT106_QSPI_A_SCK |
PORT107_QSPI_A_IO0 |
PORT108_QSPI_A_IO2 |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT128_SAI0_D2 |
PORT129_SAI0_D1 |
PORT130_SAI1_SYNC |
PORT131_CMP0_OUT |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT138_TRGMUX_OUT4 |
PORT139_TRGMUX_OUT5 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}

[!ENDVAR!]




[!VAR "CHECK_3"!]

/*  Mode PORT_ALT0_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_ADC0_SE0_CMP0_IN0 |
PORT1_ADC0_SE1_CMP0_IN1 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT6_ADC0_SE2 |
PORT7_ADC0_SE3 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          ),
/* Pads  32 ...  47 : PORT32_ADC0_SE4_ADC1_SE14 |
PORT33_ADC0_SE5_ADC1_SE15 |
PORT34_ADC0_SE6 |
PORT35_ADC0_SE7 |
PORT38_XTAL |
PORT39_EXTAL |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT45_ADC1_SE8_ADC0_SE8 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT50_ADC0_SE16 |
PORT50_ADC0_SE16 |
PORT52_ADC0_SE17 |
PORT52_ADC0_SE17 |
PORT53_ADC0_SE18 |
PORT53_ADC0_SE18 |
PORT54_ADC0_SE19 |
PORT54_ADC0_SE19 |
PORT55_ADC0_SE20 |
PORT55_ADC0_SE20 |
PORT57_ADC0_SE21 |
PORT57_ADC0_SE21 |
PORT59_ADC0_SE22 |
PORT59_ADC0_SE22 |
PORT60_ADC0_SE23 |
PORT60_ADC0_SE23 |
PORT61_ADC0_SE24 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_ADC0_SE8 |
PORT65_ADC0_SE9 |
PORT66_ADC0_SE10_CMP0_IN5 |
PORT67_ADC0_SE11_CMP0_IN4 |
PORT68_CMP0_IN2 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT78_ADC0_SE12 |
PORT79_ADC0_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_ADC0_SE14 |
PORT81_ADC0_SE15 |
PORT83_ADC0_SE25 |
PORT87_ADC0_SE26 |
PORT91_ADC0_SE27 |
PORT92_ADC0_SE28 |
PORT93_ADC0_SE29 |
PORT94_ADC0_SE30 |
PORT95_ADC0_SE31 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT102_CMP0_IN7 |
PORT103_CMP0_IN6 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7)
          ),
/* Pads 112 ... 127 : PORT114_ADC1_SE16 |
PORT114_ADC1_SE16 |
PORT115_ADC1_SE17 |
PORT115_ADC1_SE17 |
PORT118_ADC1_SE18 |
PORT118_ADC1_SE18 |
PORT119_ADC1_SE19 |
PORT119_ADC1_SE19 |
PORT120_ADC1_SE20 |
PORT120_ADC1_SE20 |
PORT123_ADC1_SE21 |
PORT123_ADC1_SE21 |
PORT124_ADC1_SE22 |
PORT124_ADC1_SE22 |
PORT125_ADC1_SE23 |
PORT125_ADC1_SE23 |
PORT126_ADC1_SE24 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT136_CMP0_IN3 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(8)
          ),
/* Pads 144 ... 159 : PORT147_ADC1_SE25 |
PORT148_ADC1_SE26 |
PORT149_ADC1_SE27 |
PORT150_ADC1_SE28 |
PORT151_ADC1_SE29 |
PORT152_ADC1_SE30 |
PORT153_ADC1_SE31 */
  (uint16)( SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT20_GPIO |
PORT21_GPIO |
PORT22_GPIO |
PORT23_GPIO |
PORT24_GPIO |
PORT25_GPIO |
PORT25_GPIO |
PORT26_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT30_GPIO |
PORT31_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT50_GPIO |
PORT50_GPIO |
PORT51_GPIO |
PORT52_GPIO |
PORT52_GPIO |
PORT53_GPIO |
PORT53_GPIO |
PORT54_GPIO |
PORT54_GPIO |
PORT55_GPIO |
PORT55_GPIO |
PORT56_GPIO |
PORT57_GPIO |
PORT57_GPIO |
PORT58_GPIO |
PORT59_GPIO |
PORT59_GPIO |
PORT60_GPIO |
PORT60_GPIO |
PORT61_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT94_GPIO |
PORT95_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT137_GPIO |
PORT138_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT148_GPIO |
PORT149_GPIO |
PORT149_GPIO |
PORT150_GPIO |
PORT150_GPIO |
PORT151_GPIO |
PORT151_GPIO |
PORT152_GPIO |
PORT152_GPIO |
PORT153_GPIO |
PORT153_GPIO |
PORT154_GPIO |
PORT155_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT1_FTM1_CH1 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT6_FTM0_FLT1 |
PORT7_FTM0_FLT2 |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT10_FTM1_CH4 |
PORT11_FTM1_CH5 |
PORT12_FTM1_CH6 |
PORT13_FTM1_CH7 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT18_FTM4_CH0 |
PORT19_FTM4_CH1 |
PORT20_FTM4_CH2 |
PORT21_FTM4_CH3 |
PORT22_FTM4_CH4 |
PORT23_FTM4_CH6 |
PORT24_FTM4_CH7 |
PORT25_FTM5_CH0 |
PORT25_FTM5_CH0 |
PORT26_FTM5_CH1 |
PORT26_FTM5_CH1 |
PORT27_FTM5_CH2 |
PORT27_FTM5_CH2 |
PORT28_FTM5_CH3 |
PORT28_FTM5_CH3 |
PORT29_FTM5_CH4 |
PORT29_FTM5_CH4 |
PORT30_FTM5_CH5 |
PORT30_FTM5_CH5 |
PORT31_FTM5_CH6 |
PORT31_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPUART0_RX |
PORT33_LPUART0_TX |
PORT34_FTM1_CH0 |
PORT35_FTM1_CH1 |
PORT36_FTM0_CH4 |
PORT37_FTM0_CH5 |
PORT38_LPI2C0_SDA |
PORT39_LPI2C0_SCL |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT44_FTM0_CH0 |
PORT45_FTM0_CH1 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT50_FTM5_CH7 |
PORT50_FTM5_CH7 |
PORT51_FTM5_CH7 |
PORT52_FTM6_CH0 |
PORT53_FTM6_CH1 |
PORT54_FTM6_CH2 |
PORT55_FTM6_CH3 |
PORT56_FTM6_CH4 |
PORT57_FTM6_CH5 |
PORT58_FTM6_CH6 |
PORT59_FTM6_CH7 |
PORT60_FTM7_CH0 |
PORT61_FTM7_CH1 |
PORT62_FTM7_CH2 |
PORT63_FTM7_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_FTM0_CH0 |
PORT65_FTM0_CH1 |
PORT66_FTM0_CH2 |
PORT67_FTM0_CH3 |
PORT68_FTM1_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT70_LPUART1_RX |
PORT71_LPUART1_TX |
PORT72_LPUART1_RX |
PORT73_LPUART1_TX |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT78_FTM1_CH2 |
PORT79_FTM1_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_FTM1_FLT2 |
PORT81_FTM1_FLT3 |
PORT82_FTM7_CH4 |
PORT83_FTM7_CH5 |
PORT84_FTM7_CH6 |
PORT85_FTM7_CH7 |
PORT86_FTM7_FLT1 |
PORT87_LPSPI0_SCK |
PORT87_LPSPI0_SCK |
PORT88_FTM4_CH0 |
PORT89_FTM4_CH1 |
PORT90_FTM4_CH3 |
PORT91_FTM4_CH4 |
PORT91_FTM4_CH4 |
PORT92_FTM4_CH7 |
PORT92_FTM4_CH7 |
PORT93_FTM5_CH2 |
PORT93_FTM5_CH2 |
PORT94_FTM5_CH4 |
PORT94_FTM5_CH4 |
PORT95_FTM5_CH6 |
PORT95_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM0_CH2 |
PORT97_FTM0_CH3 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT100_FTM0_FLT3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT104_LPI2C1_SDA |
PORT105_LPI2C1_SCL |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT111_FTM0_CH0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_FTM0_CH1 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT114_FTM5_CH7 |
PORT114_FTM5_CH7 |
PORT115_FTM6_CH0 |
PORT116_FTM6_CH1 |
PORT117_FTM6_CH2 |
PORT118_FTM6_CH3 |
PORT119_FTM6_CH4 |
PORT120_FTM6_CH5 |
PORT121_FTM6_CH6 |
PORT122_FTM6_CH7 |
PORT123_FTM7_CH0 |
PORT124_FTM7_CH1 |
PORT125_FTM7_CH2 |
PORT126_FTM7_CH3 |
PORT127_FTM7_CH4 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI0_SCK |
PORT129_LPSPI0_SIN |
PORT130_LPSPI0_SOUT |
PORT131_FTM0_FLT0 |
PORT132_ETM_TRACE_D1 |
PORT133_TCLK2 |
PORT134_LPSPI0_PCS2 |
PORT135_FTM0_CH7 |
PORT136_FTM0_CH6 |
PORT137_FTM0_CH7 |
PORT138_CLKOUT |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT141_FTM4_CH5 |
PORT141_FTM4_CH5 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT145_FTM7_CH5 |
PORT146_FTM7_CH6 |
PORT147_FTM7_CH7 |
PORT148_FTM4_CH0 |
PORT148_FTM4_CH0 |
PORT149_FTM4_CH1 |
PORT149_FTM4_CH1 |
PORT150_FTM4_CH2 |
PORT150_FTM4_CH2 |
PORT151_FTM4_CH3 |
PORT151_FTM4_CH3 |
PORT152_FTM4_CH4 |
PORT152_FTM4_CH4 |
PORT153_FTM4_CH5 |
PORT153_FTM4_CH5 |
PORT154_FTM4_CH6 |
PORT155_FTM4_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPI2C0_SCLS |
PORT1_LPI2C0_SDAS |
PORT2_LPI2C0_SDA |
PORT3_LPI2C0_SCL |
PORT5_TCLK1 |
PORT6_LPSPI1_PCS1 |
PORT7_FTM5_CH3 |
PORT7_FTM5_CH3 |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT18_LPUART1_TX |
PORT19_LPUART1_RX |
PORT21_FXIO_D0 |
PORT22_FXIO_D1 |
PORT23_FXIO_D2 |
PORT24_FXIO_D3 |
PORT26_LPSPI1_PCS0 |
PORT26_LPSPI1_PCS0 |
PORT27_LPSPI1_SOUT |
PORT27_LPSPI1_SOUT |
PORT28_LPSPI1_SCK |
PORT28_LPSPI1_SCK |
PORT30_LPUART2_RX |
PORT30_LPUART2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads  32 ...  47 : PORT32_LPSPI0_PCS0 |
PORT33_LPSPI0_SOUT |
PORT34_LPSPI0_SCK |
PORT35_LPSPI0_SIN |
PORT36_LPSPI0_SOUT |
PORT37_LPSPI0_PCS1 |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT54_MII_CRS |
PORT55_LPUART1_RX |
PORT55_LPUART1_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT66_CAN0_RX |
PORT67_CAN0_TX |
PORT68_RTC_CLKOUT |
PORT69_RTC_CLKOUT |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT72_FTM1_FLT0 |
PORT73_FTM1_FLT1 |
PORT75_FTM4_CH2 |
PORT75_FTM4_CH2 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT94_FXIO_D0 |
PORT94_FXIO_D0 |
PORT95_FXIO_D1 |
PORT95_FXIO_D1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_LPSPI1_SCK |
PORT97_LPSPI1_SIN |
PORT98_LPSPI1_SOUT |
PORT99_LPSPI1_PCS0 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT101_LPTMR0_ALT2 |
PORT104_MII_RXD3 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT108_LPI2C1_HREQ |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT111_ETM_TRACE_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_D2 |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT114_FXIO_D2 |
PORT114_FXIO_D2 |
PORT115_FXIO_D3 |
PORT115_FXIO_D3 |
PORT122_FXIO_D7 |
PORT126_FTM6_FLT1 |
PORT127_FXIO_D6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_TCLK1 |
PORT129_LPI2C0_HREQ |
PORT130_LPTMR0_ALT3 |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT134_FTM7_FLT1 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT139_LPTMR0_ALT1 |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT145_FXIO_D5 |
PORT146_FXIO_D4 |
PORT152_CAN2_TX |
PORT152_CAN2_TX |
PORT153_CAN2_RX |
PORT153_CAN2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FXIO_D2 |
PORT1_FXIO_D3 |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT4_CMP0_OUT |
PORT6_FTM5_CH5 |
PORT6_FTM5_CH5 |
PORT7_RTC_CLKIN |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT10_FXIO_D0 |
PORT11_FXIO_D1 |
PORT12_LPI2C1_SDAS |
PORT13_LPI2C1_SCLS |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT18_LPSPI1_SOUT |
PORT19_LPSPI1_SCK |
PORT20_LPSPI1_SIN |
PORT21_LPSPI1_PCS0 |
PORT22_LPSPI1_PCS1 |
PORT26_LPSPI0_PCS0 |
PORT26_LPSPI0_PCS0 |
PORT27_LPUART0_TX |
PORT27_LPUART0_TX |
PORT28_LPUART0_RX |
PORT28_LPUART0_RX |
PORT29_LPUART2_TX |
PORT29_LPUART2_TX |
PORT30_LPSPI0_SOUT |
PORT30_LPSPI0_SOUT |
PORT31_LPSPI0_PCS1 |
PORT31_LPSPI0_PCS1 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPTMR0_ALT3 |
PORT33_TCLK0 |
PORT34_FTM1_QD_PHB |
PORT35_FTM1_QD_PHA |
PORT37_LPSPI0_PCS0 |
PORT40_SAI1_BCLK |
PORT41_SAI1_D0 |
PORT42_SAI1_MCLK |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT45_CAN2_TX |
PORT45_CAN2_TX |
PORT45_CAN2_TX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT49_FTM5_FLT1 |
PORT49_FTM5_FLT1 |
PORT50_LPSPI1_PCS1 |
PORT50_LPSPI1_PCS1 |
PORT55_MII_COL */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_1 |
PORT65_MII_RMII_RXD_1 |
PORT66_LPUART0_RX |
PORT67_LPUART0_TX |
PORT69_LPI2C1_HREQ |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT72_FTM5_CH1 |
PORT72_FTM5_CH1 |
PORT73_FTM5_CH0 |
PORT73_FTM5_CH0 |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT78_MII_COL |
PORT79_MII_CRS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_LPI2C1_SDAS |
PORT81_LPI2C1_SCLS |
PORT85_FTM7_FLT0 |
PORT94_LPI2C1_SDAS |
PORT95_LPI2C1_SDA */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT98_FXIO_D4 |
PORT99_FXIO_D5 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT106_ETM_TRACE_D3 |
PORT107_ETM_TRACE_D2 |
PORT108_ETM_TRACE_D1 |
PORT111_LPSPI0_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_LPSPI0_SIN |
PORT113_FTM5_FLT1 |
PORT113_FTM5_FLT1 |
PORT114_LPI2C1_SCLS |
PORT115_LPI2C1_SCL */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3)
          ),
/* Pads 128 ... 143 : PORT128_LPI2C1_SDA |
PORT129_LPI2C1_SCL |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT140_FTM5_FLT0 |
PORT140_FTM5_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT1_FTM1_QD_PHA |
PORT2_FXIO_D4 |
PORT3_FXIO_D5 |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT11_CMP0_RRT |
PORT15_FTM7_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_FTM5_FLT0 |
PORT17_FTM5_FLT0 |
PORT18_FTM6_CH0 |
PORT27_CAN0_TX |
PORT27_CAN0_TX |
PORT28_CAN0_RX |
PORT28_CAN0_RX |
PORT29_LPSPI1_SIN |
PORT29_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  32 ...  47 : PORT32_CAN0_RX |
PORT33_CAN0_TX |
PORT36_MII_RMII_MDIO |
PORT37_CLKOUT |
PORT44_FTM6_FLT1 |
PORT45_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT54_LPUART1_TX |
PORT54_LPUART1_TX |
PORT57_LPSPI2_PCS0 |
PORT57_LPSPI2_PCS0 |
PORT59_LPSPI2_SOUT |
PORT59_LPSPI2_SOUT |
PORT60_LPSPI2_SIN |
PORT60_LPSPI2_SIN |
PORT61_LPSPI2_SCK |
PORT61_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_0 |
PORT65_MII_RMII_RXD_0 |
PORT66_MII_RMII_TXD_0 |
PORT67_MII_TX_ER |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4)
          ),
/* Pads  80 ...  95 : PORT80_MII_RMII_RX_ER |
PORT81_MII_RMII_RX_DV |
PORT83_LPSPI2_PCS1 |
PORT83_LPSPI2_PCS1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3)
          ),
/* Pads  96 ... 111 : PORT96_ETM_TRACE_D0 |
PORT97_SAI0_MCLK |
PORT98_FXIO_D6 |
PORT99_FXIO_D7 |
PORT101_MII_TXD3 |
PORT102_MII_TXD2 |
PORT103_MII_RMII_TXD_1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT105_MII_RXD2 |
PORT106_MII_RX_CLK |
PORT107_MII_RMII_TX_CLK |
PORT108_MII_RMII_TX_EN |
PORT109_ENET_TMR1 |
PORT110_ENET_TMR0 |
PORT111_ENET_TMR2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_CMP0_RRT |
PORT127_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI1_SOUT |
PORT129_LPSPI1_PCS0 |
PORT132_CAN0_RX |
PORT133_CAN0_TX |
PORT136_MII_RMII_MDC |
PORT137_ENET_TMR3 |
PORT143_FTM4_FLT1 |
PORT143_FTM4_FLT1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FTM4_FLT0 |
PORT144_FTM4_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPUART0_CTS |
PORT1_LPUART0_RTS |
PORT2_LPUART0_RX |
PORT3_LPUART0_TX |
PORT6_LPUART1_CTS |
PORT7_LPUART1_RTS |
PORT8_FTM4_FLT1 |
PORT8_FTM4_FLT1 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT11_SAI0_SYNC |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_FTM4_CH6 |
PORT32_FTM4_CH6 |
PORT33_FTM4_CH5 |
PORT33_FTM4_CH5 |
PORT34_TRGMUX_IN3 |
PORT35_TRGMUX_IN2 |
PORT36_TRGMUX_IN1 |
PORT37_TRGMUX_IN0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_FTM1_CH6 |
PORT65_FTM1_CH7 |
PORT66_ETM_TRACE_CLKOUT |
PORT67_QSPI_A_CS |
PORT68_FTM1_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT70_FTM1_QD_PHB |
PORT71_FTM1_QD_PHA |
PORT72_LPUART0_CTS |
PORT73_LPUART0_RTS |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT78_TRGMUX_IN9 |
PORT79_TRGMUX_IN8 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT96_FXIO_D0 |
PORT97_FXIO_D1 |
PORT98_TRGMUX_IN5 |
PORT99_TRGMUX_IN4 |
PORT101_TRGMUX_IN7 |
PORT103_ETM_TRACE_D0 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT106_CLKOUT |
PORT106_CLKOUT |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_CLKOUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 : PORT128_FTM1_FLT2 |
PORT129_FTM1_FLT1 |
PORT130_LPUART1_CTS |
PORT131_TRGMUX_IN6 |
PORT132_FXIO_D6 |
PORT133_FXIO_D7 |
PORT134_LPUART1_RTS |
PORT138_FXIO_D4 |
PORT139_FXIO_D5 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_TRGMUX_OUT3 |
PORT1_TRGMUX_OUT0 |
PORT4_JTAG_TMS_SWD_DIO |
PORT5_RESET_b |
PORT9_FTM4_FLT0 |
PORT9_FTM4_FLT0 |
PORT10_JTAG_TDO |
PORT12_SAI0_BCLK |
PORT13_SAI0_D0 |
PORT14_SAI0_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT36_QSPI_B_IO0 |
PORT37_MII_RMII_MDC */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_QSPI_B_RWDS |
PORT65_QSPI_B_SCK |
PORT66_QSPI_A_IO3 |
PORT67_QSPI_B_IO3 |
PORT68_JTAG_TCLK_SWD_CLK |
PORT69_JTAG_TDI |
PORT79_QSPI_B_CS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_QSPI_B_IO7 |
PORT81_QSPI_B_IO6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1)
          ),
/* Pads  96 ... 111 : PORT96_TRGMUX_OUT1 |
PORT97_TRGMUX_OUT2 |
PORT99_NMI_b |
PORT101_QSPI_B_IO2 |
PORT102_QSPI_B_IO1 |
PORT103_QSPI_A_IO1 |
PORT104_QSPI_B_IO5 |
PORT105_QSPI_B_IO4 |
PORT106_QSPI_A_SCK |
PORT107_QSPI_A_IO0 |
PORT108_QSPI_A_IO2 |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT128_SAI0_D2 |
PORT129_SAI0_D1 |
PORT130_SAI1_SYNC |
PORT131_CMP0_OUT |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT138_TRGMUX_OUT4 |
PORT139_TRGMUX_OUT5 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}

[!ENDVAR!]




[!VAR "CHECK_4"!]

/*  Mode PORT_ALT0_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_ADC0_SE0_CMP0_IN0 |
PORT1_ADC0_SE1_CMP0_IN1 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT6_ADC0_SE2 |
PORT7_ADC0_SE3 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          ),
/* Pads  32 ...  47 : PORT32_ADC0_SE4_ADC1_SE14 |
PORT33_ADC0_SE5_ADC1_SE15 |
PORT34_ADC0_SE6 |
PORT35_ADC0_SE7 |
PORT38_XTAL |
PORT39_EXTAL |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT45_ADC1_SE8_ADC0_SE8 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT50_ADC0_SE16 |
PORT50_ADC0_SE16 |
PORT52_ADC0_SE17 |
PORT52_ADC0_SE17 |
PORT53_ADC0_SE18 |
PORT53_ADC0_SE18 |
PORT54_ADC0_SE19 |
PORT54_ADC0_SE19 |
PORT55_ADC0_SE20 |
PORT55_ADC0_SE20 |
PORT57_ADC0_SE21 |
PORT57_ADC0_SE21 |
PORT59_ADC0_SE22 |
PORT59_ADC0_SE22 |
PORT60_ADC0_SE23 |
PORT60_ADC0_SE23 |
PORT61_ADC0_SE24 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_ADC0_SE8 |
PORT65_ADC0_SE9 |
PORT66_ADC0_SE10_CMP0_IN5 |
PORT67_ADC0_SE11_CMP0_IN4 |
PORT68_CMP0_IN2 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT78_ADC0_SE12 |
PORT79_ADC0_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_ADC0_SE14 |
PORT81_ADC0_SE15 |
PORT83_ADC0_SE25 |
PORT87_ADC0_SE26 |
PORT91_ADC0_SE27 |
PORT92_ADC0_SE28 |
PORT93_ADC0_SE29 |
PORT94_ADC0_SE30 |
PORT95_ADC0_SE31 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT102_CMP0_IN7 |
PORT103_CMP0_IN6 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7)
          ),
/* Pads 112 ... 127 : PORT114_ADC1_SE16 |
PORT114_ADC1_SE16 |
PORT115_ADC1_SE17 |
PORT115_ADC1_SE17 |
PORT118_ADC1_SE18 |
PORT118_ADC1_SE18 |
PORT119_ADC1_SE19 |
PORT119_ADC1_SE19 |
PORT120_ADC1_SE20 |
PORT120_ADC1_SE20 |
PORT123_ADC1_SE21 |
PORT123_ADC1_SE21 |
PORT124_ADC1_SE22 |
PORT124_ADC1_SE22 |
PORT125_ADC1_SE23 |
PORT125_ADC1_SE23 |
PORT126_ADC1_SE24 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT136_CMP0_IN3 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(8)
          ),
/* Pads 144 ... 159 : PORT147_ADC1_SE25 |
PORT148_ADC1_SE26 |
PORT149_ADC1_SE27 |
PORT150_ADC1_SE28 |
PORT151_ADC1_SE29 |
PORT152_ADC1_SE30 |
PORT153_ADC1_SE31 */
  (uint16)( SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT20_GPIO |
PORT21_GPIO |
PORT22_GPIO |
PORT23_GPIO |
PORT24_GPIO |
PORT25_GPIO |
PORT25_GPIO |
PORT26_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT30_GPIO |
PORT31_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT50_GPIO |
PORT50_GPIO |
PORT51_GPIO |
PORT52_GPIO |
PORT52_GPIO |
PORT53_GPIO |
PORT53_GPIO |
PORT54_GPIO |
PORT54_GPIO |
PORT55_GPIO |
PORT55_GPIO |
PORT56_GPIO |
PORT57_GPIO |
PORT57_GPIO |
PORT58_GPIO |
PORT59_GPIO |
PORT59_GPIO |
PORT60_GPIO |
PORT60_GPIO |
PORT61_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT94_GPIO |
PORT95_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT137_GPIO |
PORT138_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT148_GPIO |
PORT149_GPIO |
PORT149_GPIO |
PORT150_GPIO |
PORT150_GPIO |
PORT151_GPIO |
PORT151_GPIO |
PORT152_GPIO |
PORT152_GPIO |
PORT153_GPIO |
PORT153_GPIO |
PORT154_GPIO |
PORT155_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT1_FTM1_CH1 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT6_FTM0_FLT1 |
PORT7_FTM0_FLT2 |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT10_FTM1_CH4 |
PORT11_FTM1_CH5 |
PORT12_FTM1_CH6 |
PORT13_FTM1_CH7 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT18_FTM4_CH0 |
PORT19_FTM4_CH1 |
PORT20_FTM4_CH2 |
PORT21_FTM4_CH3 |
PORT22_FTM4_CH4 |
PORT23_FTM4_CH6 |
PORT24_FTM4_CH7 |
PORT25_FTM5_CH0 |
PORT25_FTM5_CH0 |
PORT26_FTM5_CH1 |
PORT26_FTM5_CH1 |
PORT27_FTM5_CH2 |
PORT27_FTM5_CH2 |
PORT28_FTM5_CH3 |
PORT28_FTM5_CH3 |
PORT29_FTM5_CH4 |
PORT29_FTM5_CH4 |
PORT30_FTM5_CH5 |
PORT30_FTM5_CH5 |
PORT31_FTM5_CH6 |
PORT31_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPUART0_RX |
PORT33_LPUART0_TX |
PORT34_FTM1_CH0 |
PORT35_FTM1_CH1 |
PORT36_FTM0_CH4 |
PORT37_FTM0_CH5 |
PORT38_LPI2C0_SDA |
PORT39_LPI2C0_SCL |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT44_FTM0_CH0 |
PORT45_FTM0_CH1 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT50_FTM5_CH7 |
PORT50_FTM5_CH7 |
PORT51_FTM5_CH7 |
PORT52_FTM6_CH0 |
PORT53_FTM6_CH1 |
PORT54_FTM6_CH2 |
PORT55_FTM6_CH3 |
PORT56_FTM6_CH4 |
PORT57_FTM6_CH5 |
PORT58_FTM6_CH6 |
PORT59_FTM6_CH7 |
PORT60_FTM7_CH0 |
PORT61_FTM7_CH1 |
PORT62_FTM7_CH2 |
PORT63_FTM7_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_FTM0_CH0 |
PORT65_FTM0_CH1 |
PORT66_FTM0_CH2 |
PORT67_FTM0_CH3 |
PORT68_FTM1_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT70_LPUART1_RX |
PORT71_LPUART1_TX |
PORT72_LPUART1_RX |
PORT73_LPUART1_TX |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT78_FTM1_CH2 |
PORT79_FTM1_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_FTM1_FLT2 |
PORT81_FTM1_FLT3 |
PORT82_FTM7_CH4 |
PORT83_FTM7_CH5 |
PORT84_FTM7_CH6 |
PORT85_FTM7_CH7 |
PORT86_FTM7_FLT1 |
PORT87_LPSPI0_SCK |
PORT87_LPSPI0_SCK |
PORT88_FTM4_CH0 |
PORT89_FTM4_CH1 |
PORT90_FTM4_CH3 |
PORT91_FTM4_CH4 |
PORT91_FTM4_CH4 |
PORT92_FTM4_CH7 |
PORT92_FTM4_CH7 |
PORT93_FTM5_CH2 |
PORT93_FTM5_CH2 |
PORT94_FTM5_CH4 |
PORT94_FTM5_CH4 |
PORT95_FTM5_CH6 |
PORT95_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM0_CH2 |
PORT97_FTM0_CH3 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT100_FTM0_FLT3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT104_LPI2C1_SDA |
PORT105_LPI2C1_SCL |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT111_FTM0_CH0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_FTM0_CH1 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT114_FTM5_CH7 |
PORT114_FTM5_CH7 |
PORT115_FTM6_CH0 |
PORT116_FTM6_CH1 |
PORT117_FTM6_CH2 |
PORT118_FTM6_CH3 |
PORT119_FTM6_CH4 |
PORT120_FTM6_CH5 |
PORT121_FTM6_CH6 |
PORT122_FTM6_CH7 |
PORT123_FTM7_CH0 |
PORT124_FTM7_CH1 |
PORT125_FTM7_CH2 |
PORT126_FTM7_CH3 |
PORT127_FTM7_CH4 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI0_SCK |
PORT129_LPSPI0_SIN |
PORT130_LPSPI0_SOUT |
PORT131_FTM0_FLT0 |
PORT132_ETM_TRACE_D1 |
PORT133_TCLK2 |
PORT134_LPSPI0_PCS2 |
PORT135_FTM0_CH7 |
PORT136_FTM0_CH6 |
PORT137_FTM0_CH7 |
PORT138_CLKOUT |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT141_FTM4_CH5 |
PORT141_FTM4_CH5 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT145_FTM7_CH5 |
PORT146_FTM7_CH6 |
PORT147_FTM7_CH7 |
PORT148_FTM4_CH0 |
PORT148_FTM4_CH0 |
PORT149_FTM4_CH1 |
PORT149_FTM4_CH1 |
PORT150_FTM4_CH2 |
PORT150_FTM4_CH2 |
PORT151_FTM4_CH3 |
PORT151_FTM4_CH3 |
PORT152_FTM4_CH4 |
PORT152_FTM4_CH4 |
PORT153_FTM4_CH5 |
PORT153_FTM4_CH5 |
PORT154_FTM4_CH6 |
PORT155_FTM4_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPI2C0_SCLS |
PORT1_LPI2C0_SDAS |
PORT2_LPI2C0_SDA |
PORT3_LPI2C0_SCL |
PORT5_TCLK1 |
PORT6_LPSPI1_PCS1 |
PORT7_FTM5_CH3 |
PORT7_FTM5_CH3 |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT18_LPUART1_TX |
PORT19_LPUART1_RX |
PORT21_FXIO_D0 |
PORT22_FXIO_D1 |
PORT23_FXIO_D2 |
PORT24_FXIO_D3 |
PORT26_LPSPI1_PCS0 |
PORT26_LPSPI1_PCS0 |
PORT27_LPSPI1_SOUT |
PORT27_LPSPI1_SOUT |
PORT28_LPSPI1_SCK |
PORT28_LPSPI1_SCK |
PORT30_LPUART2_RX |
PORT30_LPUART2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads  32 ...  47 : PORT32_LPSPI0_PCS0 |
PORT33_LPSPI0_SOUT |
PORT34_LPSPI0_SCK |
PORT35_LPSPI0_SIN |
PORT36_LPSPI0_SOUT |
PORT37_LPSPI0_PCS1 |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT54_MII_CRS |
PORT55_LPUART1_RX |
PORT55_LPUART1_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT66_CAN0_RX |
PORT67_CAN0_TX |
PORT68_RTC_CLKOUT |
PORT69_RTC_CLKOUT |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT72_FTM1_FLT0 |
PORT73_FTM1_FLT1 |
PORT75_FTM4_CH2 |
PORT75_FTM4_CH2 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT94_FXIO_D0 |
PORT94_FXIO_D0 |
PORT95_FXIO_D1 |
PORT95_FXIO_D1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_LPSPI1_SCK |
PORT97_LPSPI1_SIN |
PORT98_LPSPI1_SOUT |
PORT99_LPSPI1_PCS0 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT101_LPTMR0_ALT2 |
PORT104_MII_RXD3 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT108_LPI2C1_HREQ |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT111_ETM_TRACE_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_D2 |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT114_FXIO_D2 |
PORT114_FXIO_D2 |
PORT115_FXIO_D3 |
PORT115_FXIO_D3 |
PORT122_FXIO_D7 |
PORT126_FTM6_FLT1 |
PORT127_FXIO_D6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_TCLK1 |
PORT129_LPI2C0_HREQ |
PORT130_LPTMR0_ALT3 |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT134_FTM7_FLT1 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT139_LPTMR0_ALT1 |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT145_FXIO_D5 |
PORT146_FXIO_D4 |
PORT152_CAN2_TX |
PORT152_CAN2_TX |
PORT153_CAN2_RX |
PORT153_CAN2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FXIO_D2 |
PORT1_FXIO_D3 |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT4_CMP0_OUT |
PORT6_FTM5_CH5 |
PORT6_FTM5_CH5 |
PORT7_RTC_CLKIN |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT10_FXIO_D0 |
PORT11_FXIO_D1 |
PORT12_LPI2C1_SDAS |
PORT13_LPI2C1_SCLS |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT18_LPSPI1_SOUT |
PORT19_LPSPI1_SCK |
PORT20_LPSPI1_SIN |
PORT21_LPSPI1_PCS0 |
PORT22_LPSPI1_PCS1 |
PORT26_LPSPI0_PCS0 |
PORT26_LPSPI0_PCS0 |
PORT27_LPUART0_TX |
PORT27_LPUART0_TX |
PORT28_LPUART0_RX |
PORT28_LPUART0_RX |
PORT29_LPUART2_TX |
PORT29_LPUART2_TX |
PORT30_LPSPI0_SOUT |
PORT30_LPSPI0_SOUT |
PORT31_LPSPI0_PCS1 |
PORT31_LPSPI0_PCS1 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPTMR0_ALT3 |
PORT33_TCLK0 |
PORT34_FTM1_QD_PHB |
PORT35_FTM1_QD_PHA |
PORT37_LPSPI0_PCS0 |
PORT40_SAI1_BCLK |
PORT41_SAI1_D0 |
PORT42_SAI1_MCLK |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT45_CAN2_TX |
PORT45_CAN2_TX |
PORT45_CAN2_TX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT49_FTM5_FLT1 |
PORT49_FTM5_FLT1 |
PORT50_LPSPI1_PCS1 |
PORT50_LPSPI1_PCS1 |
PORT55_MII_COL */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_1 |
PORT65_MII_RMII_RXD_1 |
PORT66_LPUART0_RX |
PORT67_LPUART0_TX |
PORT69_LPI2C1_HREQ |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT72_FTM5_CH1 |
PORT72_FTM5_CH1 |
PORT73_FTM5_CH0 |
PORT73_FTM5_CH0 |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT78_MII_COL |
PORT79_MII_CRS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_LPI2C1_SDAS |
PORT81_LPI2C1_SCLS |
PORT85_FTM7_FLT0 |
PORT94_LPI2C1_SDAS |
PORT95_LPI2C1_SDA */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT98_FXIO_D4 |
PORT99_FXIO_D5 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT106_ETM_TRACE_D3 |
PORT107_ETM_TRACE_D2 |
PORT108_ETM_TRACE_D1 |
PORT111_LPSPI0_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_LPSPI0_SIN |
PORT113_FTM5_FLT1 |
PORT113_FTM5_FLT1 |
PORT114_LPI2C1_SCLS |
PORT115_LPI2C1_SCL */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3)
          ),
/* Pads 128 ... 143 : PORT128_LPI2C1_SDA |
PORT129_LPI2C1_SCL |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT140_FTM5_FLT0 |
PORT140_FTM5_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT1_FTM1_QD_PHA |
PORT2_FXIO_D4 |
PORT3_FXIO_D5 |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT11_CMP0_RRT |
PORT15_FTM7_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_FTM5_FLT0 |
PORT17_FTM5_FLT0 |
PORT18_FTM6_CH0 |
PORT27_CAN0_TX |
PORT27_CAN0_TX |
PORT28_CAN0_RX |
PORT28_CAN0_RX |
PORT29_LPSPI1_SIN |
PORT29_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  32 ...  47 : PORT32_CAN0_RX |
PORT33_CAN0_TX |
PORT36_MII_RMII_MDIO |
PORT37_CLKOUT |
PORT44_FTM6_FLT1 |
PORT45_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT54_LPUART1_TX |
PORT54_LPUART1_TX |
PORT57_LPSPI2_PCS0 |
PORT57_LPSPI2_PCS0 |
PORT59_LPSPI2_SOUT |
PORT59_LPSPI2_SOUT |
PORT60_LPSPI2_SIN |
PORT60_LPSPI2_SIN |
PORT61_LPSPI2_SCK |
PORT61_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_0 |
PORT65_MII_RMII_RXD_0 |
PORT66_MII_RMII_TXD_0 |
PORT67_MII_TX_ER |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4)
          ),
/* Pads  80 ...  95 : PORT80_MII_RMII_RX_ER |
PORT81_MII_RMII_RX_DV |
PORT83_LPSPI2_PCS1 |
PORT83_LPSPI2_PCS1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3)
          ),
/* Pads  96 ... 111 : PORT96_ETM_TRACE_D0 |
PORT97_SAI0_MCLK |
PORT98_FXIO_D6 |
PORT99_FXIO_D7 |
PORT101_MII_TXD3 |
PORT102_MII_TXD2 |
PORT103_MII_RMII_TXD_1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT105_MII_RXD2 |
PORT106_MII_RX_CLK |
PORT107_MII_RMII_TX_CLK |
PORT108_MII_RMII_TX_EN |
PORT109_ENET_TMR1 |
PORT110_ENET_TMR0 |
PORT111_ENET_TMR2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_CMP0_RRT |
PORT127_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI1_SOUT |
PORT129_LPSPI1_PCS0 |
PORT132_CAN0_RX |
PORT133_CAN0_TX |
PORT136_MII_RMII_MDC |
PORT137_ENET_TMR3 |
PORT143_FTM4_FLT1 |
PORT143_FTM4_FLT1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FTM4_FLT0 |
PORT144_FTM4_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPUART0_CTS |
PORT1_LPUART0_RTS |
PORT2_LPUART0_RX |
PORT3_LPUART0_TX |
PORT6_LPUART1_CTS |
PORT7_LPUART1_RTS |
PORT8_FTM4_FLT1 |
PORT8_FTM4_FLT1 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT11_SAI0_SYNC |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_FTM4_CH6 |
PORT32_FTM4_CH6 |
PORT33_FTM4_CH5 |
PORT33_FTM4_CH5 |
PORT34_TRGMUX_IN3 |
PORT35_TRGMUX_IN2 |
PORT36_TRGMUX_IN1 |
PORT37_TRGMUX_IN0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_FTM1_CH6 |
PORT65_FTM1_CH7 |
PORT66_ETM_TRACE_CLKOUT |
PORT67_QSPI_A_CS |
PORT68_FTM1_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT70_FTM1_QD_PHB |
PORT71_FTM1_QD_PHA |
PORT72_LPUART0_CTS |
PORT73_LPUART0_RTS |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT78_TRGMUX_IN9 |
PORT79_TRGMUX_IN8 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT96_FXIO_D0 |
PORT97_FXIO_D1 |
PORT98_TRGMUX_IN5 |
PORT99_TRGMUX_IN4 |
PORT101_TRGMUX_IN7 |
PORT103_ETM_TRACE_D0 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT106_CLKOUT |
PORT106_CLKOUT |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_CLKOUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 : PORT128_FTM1_FLT2 |
PORT129_FTM1_FLT1 |
PORT130_LPUART1_CTS |
PORT131_TRGMUX_IN6 |
PORT132_FXIO_D6 |
PORT133_FXIO_D7 |
PORT134_LPUART1_RTS |
PORT138_FXIO_D4 |
PORT139_FXIO_D5 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_TRGMUX_OUT3 |
PORT1_TRGMUX_OUT0 |
PORT4_JTAG_TMS_SWD_DIO |
PORT5_RESET_b |
PORT9_FTM4_FLT0 |
PORT9_FTM4_FLT0 |
PORT10_JTAG_TDO |
PORT12_SAI0_BCLK |
PORT13_SAI0_D0 |
PORT14_SAI0_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT36_QSPI_B_IO0 |
PORT37_MII_RMII_MDC */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_QSPI_B_RWDS |
PORT65_QSPI_B_SCK |
PORT66_QSPI_A_IO3 |
PORT67_QSPI_B_IO3 |
PORT68_JTAG_TCLK_SWD_CLK |
PORT69_JTAG_TDI |
PORT79_QSPI_B_CS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_QSPI_B_IO7 |
PORT81_QSPI_B_IO6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1)
          ),
/* Pads  96 ... 111 : PORT96_TRGMUX_OUT1 |
PORT97_TRGMUX_OUT2 |
PORT99_NMI_b |
PORT101_QSPI_B_IO2 |
PORT102_QSPI_B_IO1 |
PORT103_QSPI_A_IO1 |
PORT104_QSPI_B_IO5 |
PORT105_QSPI_B_IO4 |
PORT106_QSPI_A_SCK |
PORT107_QSPI_A_IO0 |
PORT108_QSPI_A_IO2 |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT128_SAI0_D2 |
PORT129_SAI0_D1 |
PORT130_SAI1_SYNC |
PORT131_CMP0_OUT |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT138_TRGMUX_OUT4 |
PORT139_TRGMUX_OUT5 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}

[!ENDVAR!]




[!VAR "CHECK_5"!]

/*  Mode PORT_ALT0_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_ADC0_SE0_CMP0_IN0 |
PORT1_ADC0_SE1_CMP0_IN1 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT6_ADC0_SE2 |
PORT7_ADC0_SE3 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          ),
/* Pads  32 ...  47 : PORT32_ADC0_SE4_ADC1_SE14 |
PORT33_ADC0_SE5_ADC1_SE15 |
PORT34_ADC0_SE6 |
PORT35_ADC0_SE7 |
PORT38_XTAL |
PORT39_EXTAL |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT45_ADC1_SE8_ADC0_SE8 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT50_ADC0_SE16 |
PORT50_ADC0_SE16 |
PORT52_ADC0_SE17 |
PORT52_ADC0_SE17 |
PORT53_ADC0_SE18 |
PORT53_ADC0_SE18 |
PORT54_ADC0_SE19 |
PORT54_ADC0_SE19 |
PORT55_ADC0_SE20 |
PORT55_ADC0_SE20 |
PORT57_ADC0_SE21 |
PORT57_ADC0_SE21 |
PORT59_ADC0_SE22 |
PORT59_ADC0_SE22 |
PORT60_ADC0_SE23 |
PORT60_ADC0_SE23 |
PORT61_ADC0_SE24 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_ADC0_SE8 |
PORT65_ADC0_SE9 |
PORT66_ADC0_SE10_CMP0_IN5 |
PORT67_ADC0_SE11_CMP0_IN4 |
PORT68_CMP0_IN2 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT78_ADC0_SE12 |
PORT79_ADC0_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_ADC0_SE14 |
PORT81_ADC0_SE15 |
PORT83_ADC0_SE25 |
PORT87_ADC0_SE26 |
PORT91_ADC0_SE27 |
PORT92_ADC0_SE28 |
PORT93_ADC0_SE29 |
PORT94_ADC0_SE30 |
PORT95_ADC0_SE31 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT102_CMP0_IN7 |
PORT103_CMP0_IN6 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7)
          ),
/* Pads 112 ... 127 : PORT114_ADC1_SE16 |
PORT114_ADC1_SE16 |
PORT115_ADC1_SE17 |
PORT115_ADC1_SE17 |
PORT118_ADC1_SE18 |
PORT118_ADC1_SE18 |
PORT119_ADC1_SE19 |
PORT119_ADC1_SE19 |
PORT120_ADC1_SE20 |
PORT120_ADC1_SE20 |
PORT123_ADC1_SE21 |
PORT123_ADC1_SE21 |
PORT124_ADC1_SE22 |
PORT124_ADC1_SE22 |
PORT125_ADC1_SE23 |
PORT125_ADC1_SE23 |
PORT126_ADC1_SE24 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT130_ADC1_SE10 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT134_ADC1_SE11 |
PORT136_CMP0_IN3 */
  (uint16)( SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(8)
          ),
/* Pads 144 ... 159 : PORT147_ADC1_SE25 |
PORT148_ADC1_SE26 |
PORT149_ADC1_SE27 |
PORT150_ADC1_SE28 |
PORT151_ADC1_SE29 |
PORT152_ADC1_SE30 |
PORT153_ADC1_SE31 */
  (uint16)( SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT20_GPIO |
PORT21_GPIO |
PORT22_GPIO |
PORT23_GPIO |
PORT24_GPIO |
PORT25_GPIO |
PORT25_GPIO |
PORT26_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT30_GPIO |
PORT31_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT50_GPIO |
PORT50_GPIO |
PORT51_GPIO |
PORT52_GPIO |
PORT52_GPIO |
PORT53_GPIO |
PORT53_GPIO |
PORT54_GPIO |
PORT54_GPIO |
PORT55_GPIO |
PORT55_GPIO |
PORT56_GPIO |
PORT57_GPIO |
PORT57_GPIO |
PORT58_GPIO |
PORT59_GPIO |
PORT59_GPIO |
PORT60_GPIO |
PORT60_GPIO |
PORT61_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT94_GPIO |
PORT95_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT137_GPIO |
PORT138_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT142_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT148_GPIO |
PORT149_GPIO |
PORT149_GPIO |
PORT150_GPIO |
PORT150_GPIO |
PORT151_GPIO |
PORT151_GPIO |
PORT152_GPIO |
PORT152_GPIO |
PORT153_GPIO |
PORT153_GPIO |
PORT154_GPIO |
PORT155_GPIO */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT1_FTM1_CH1 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT6_FTM0_FLT1 |
PORT7_FTM0_FLT2 |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT10_FTM1_CH4 |
PORT11_FTM1_CH5 |
PORT12_FTM1_CH6 |
PORT13_FTM1_CH7 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT18_FTM4_CH0 |
PORT19_FTM4_CH1 |
PORT20_FTM4_CH2 |
PORT21_FTM4_CH3 |
PORT22_FTM4_CH4 |
PORT23_FTM4_CH6 |
PORT24_FTM4_CH7 |
PORT25_FTM5_CH0 |
PORT25_FTM5_CH0 |
PORT26_FTM5_CH1 |
PORT26_FTM5_CH1 |
PORT27_FTM5_CH2 |
PORT27_FTM5_CH2 |
PORT28_FTM5_CH3 |
PORT28_FTM5_CH3 |
PORT29_FTM5_CH4 |
PORT29_FTM5_CH4 |
PORT30_FTM5_CH5 |
PORT30_FTM5_CH5 |
PORT31_FTM5_CH6 |
PORT31_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPUART0_RX |
PORT33_LPUART0_TX |
PORT34_FTM1_CH0 |
PORT35_FTM1_CH1 |
PORT36_FTM0_CH4 |
PORT37_FTM0_CH5 |
PORT38_LPI2C0_SDA |
PORT39_LPI2C0_SCL |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT44_FTM0_CH0 |
PORT45_FTM0_CH1 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT50_FTM5_CH7 |
PORT50_FTM5_CH7 |
PORT51_FTM5_CH7 |
PORT52_FTM6_CH0 |
PORT53_FTM6_CH1 |
PORT54_FTM6_CH2 |
PORT55_FTM6_CH3 |
PORT56_FTM6_CH4 |
PORT57_FTM6_CH5 |
PORT58_FTM6_CH6 |
PORT59_FTM6_CH7 |
PORT60_FTM7_CH0 |
PORT61_FTM7_CH1 |
PORT62_FTM7_CH2 |
PORT63_FTM7_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_FTM0_CH0 |
PORT65_FTM0_CH1 |
PORT66_FTM0_CH2 |
PORT67_FTM0_CH3 |
PORT68_FTM1_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT70_LPUART1_RX |
PORT71_LPUART1_TX |
PORT72_LPUART1_RX |
PORT73_LPUART1_TX |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT78_FTM1_CH2 |
PORT79_FTM1_CH3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_FTM1_FLT2 |
PORT81_FTM1_FLT3 |
PORT82_FTM7_CH4 |
PORT83_FTM7_CH5 |
PORT84_FTM7_CH6 |
PORT85_FTM7_CH7 |
PORT86_FTM7_FLT1 |
PORT87_LPSPI0_SCK |
PORT87_LPSPI0_SCK |
PORT88_FTM4_CH0 |
PORT89_FTM4_CH1 |
PORT90_FTM4_CH3 |
PORT91_FTM4_CH4 |
PORT91_FTM4_CH4 |
PORT92_FTM4_CH7 |
PORT92_FTM4_CH7 |
PORT93_FTM5_CH2 |
PORT93_FTM5_CH2 |
PORT94_FTM5_CH4 |
PORT94_FTM5_CH4 |
PORT95_FTM5_CH6 |
PORT95_FTM5_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM0_CH2 |
PORT97_FTM0_CH3 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT98_FTM3_CH4 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT99_FTM3_CH5 |
PORT100_FTM0_FLT3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT101_FTM2_CH3 |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT102_LPUART2_RX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT103_LPUART2_TX |
PORT104_LPI2C1_SDA |
PORT105_LPI2C1_SCL |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT106_FTM2_CH0 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT107_FTM2_CH1 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT108_FTM2_CH2 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT109_FTM2_CH4 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT110_FTM2_CH5 |
PORT111_FTM0_CH0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_FTM0_CH1 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT113_FTM0_FLT2 |
PORT114_FTM5_CH7 |
PORT114_FTM5_CH7 |
PORT115_FTM6_CH0 |
PORT116_FTM6_CH1 |
PORT117_FTM6_CH2 |
PORT118_FTM6_CH3 |
PORT119_FTM6_CH4 |
PORT120_FTM6_CH5 |
PORT121_FTM6_CH6 |
PORT122_FTM6_CH7 |
PORT123_FTM7_CH0 |
PORT124_FTM7_CH1 |
PORT125_FTM7_CH2 |
PORT126_FTM7_CH3 |
PORT127_FTM7_CH4 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI0_SCK |
PORT129_LPSPI0_SIN |
PORT130_LPSPI0_SOUT |
PORT131_FTM0_FLT0 |
PORT132_ETM_TRACE_D1 |
PORT133_TCLK2 |
PORT134_LPSPI0_PCS2 |
PORT135_FTM0_CH7 |
PORT136_FTM0_CH6 |
PORT137_FTM0_CH7 |
PORT138_CLKOUT |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT139_LPSPI2_PCS0 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT140_FTM0_FLT3 |
PORT141_FTM4_CH5 |
PORT141_FTM4_CH5 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT142_FTM0_FLT1 |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS |
PORT143_LPUART1_CTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT144_LPUART1_RTS |
PORT145_FTM7_CH5 |
PORT146_FTM7_CH6 |
PORT147_FTM7_CH7 |
PORT148_FTM4_CH0 |
PORT148_FTM4_CH0 |
PORT149_FTM4_CH1 |
PORT149_FTM4_CH1 |
PORT150_FTM4_CH2 |
PORT150_FTM4_CH2 |
PORT151_FTM4_CH3 |
PORT151_FTM4_CH3 |
PORT152_FTM4_CH4 |
PORT152_FTM4_CH4 |
PORT153_FTM4_CH5 |
PORT153_FTM4_CH5 |
PORT154_FTM4_CH6 |
PORT155_FTM4_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPI2C0_SCLS |
PORT1_LPI2C0_SDAS |
PORT2_LPI2C0_SDA |
PORT3_LPI2C0_SCL |
PORT5_TCLK1 |
PORT6_LPSPI1_PCS1 |
PORT7_FTM5_CH3 |
PORT7_FTM5_CH3 |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT18_LPUART1_TX |
PORT19_LPUART1_RX |
PORT21_FXIO_D0 |
PORT22_FXIO_D1 |
PORT23_FXIO_D2 |
PORT24_FXIO_D3 |
PORT26_LPSPI1_PCS0 |
PORT26_LPSPI1_PCS0 |
PORT27_LPSPI1_SOUT |
PORT27_LPSPI1_SOUT |
PORT28_LPSPI1_SCK |
PORT28_LPSPI1_SCK |
PORT30_LPUART2_RX |
PORT30_LPUART2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads  32 ...  47 : PORT32_LPSPI0_PCS0 |
PORT33_LPSPI0_SOUT |
PORT34_LPSPI0_SCK |
PORT35_LPSPI0_SIN |
PORT36_LPSPI0_SOUT |
PORT37_LPSPI0_PCS1 |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT54_MII_CRS |
PORT55_LPUART1_RX |
PORT55_LPUART1_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT66_CAN0_RX |
PORT67_CAN0_TX |
PORT68_RTC_CLKOUT |
PORT69_RTC_CLKOUT |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT72_FTM1_FLT0 |
PORT73_FTM1_FLT1 |
PORT75_FTM4_CH2 |
PORT75_FTM4_CH2 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT80_CAN2_RX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT81_CAN2_TX |
PORT94_FXIO_D0 |
PORT94_FXIO_D0 |
PORT95_FXIO_D1 |
PORT95_FXIO_D1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_LPSPI1_SCK |
PORT97_LPSPI1_SIN |
PORT98_LPSPI1_SOUT |
PORT99_LPSPI1_PCS0 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT100_FTM3_FLT3 |
PORT101_LPTMR0_ALT2 |
PORT104_MII_RXD3 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT105_FXIO_D0 |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT106_FTM2_QD_PHB |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT107_FTM2_QD_PHA |
PORT108_LPI2C1_HREQ |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT109_LPUART1_RX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT110_LPUART1_TX |
PORT111_ETM_TRACE_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_D2 |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT113_LPUART2_RX |
PORT114_FXIO_D2 |
PORT114_FXIO_D2 |
PORT115_FXIO_D3 |
PORT115_FXIO_D3 |
PORT122_FXIO_D7 |
PORT126_FTM6_FLT1 |
PORT127_FXIO_D6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_TCLK1 |
PORT129_LPI2C0_HREQ |
PORT130_LPTMR0_ALT3 |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT131_LPUART2_RTS |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT132_FTM2_QD_PHB |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT133_FTM2_QD_PHA |
PORT134_FTM7_FLT1 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT135_FTM3_FLT0 |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT137_LPUART2_CTS |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT138_LPSPI2_PCS1 |
PORT139_LPTMR0_ALT1 |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT140_LPUART2_TX |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT141_LPSPI2_PCS2 |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK |
PORT143_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT144_LPSPI2_SIN |
PORT145_FXIO_D5 |
PORT146_FXIO_D4 |
PORT152_CAN2_TX |
PORT152_CAN2_TX |
PORT153_CAN2_RX |
PORT153_CAN2_RX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FXIO_D2 |
PORT1_FXIO_D3 |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT4_CMP0_OUT |
PORT6_FTM5_CH5 |
PORT6_FTM5_CH5 |
PORT7_RTC_CLKIN |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT10_FXIO_D0 |
PORT11_FXIO_D1 |
PORT12_LPI2C1_SDAS |
PORT13_LPI2C1_SCLS |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT18_LPSPI1_SOUT |
PORT19_LPSPI1_SCK |
PORT20_LPSPI1_SIN |
PORT21_LPSPI1_PCS0 |
PORT22_LPSPI1_PCS1 |
PORT26_LPSPI0_PCS0 |
PORT26_LPSPI0_PCS0 |
PORT27_LPUART0_TX |
PORT27_LPUART0_TX |
PORT28_LPUART0_RX |
PORT28_LPUART0_RX |
PORT29_LPUART2_TX |
PORT29_LPUART2_TX |
PORT30_LPSPI0_SOUT |
PORT30_LPSPI0_SOUT |
PORT31_LPSPI0_PCS1 |
PORT31_LPSPI0_PCS1 */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_LPTMR0_ALT3 |
PORT33_TCLK0 |
PORT34_FTM1_QD_PHB |
PORT35_FTM1_QD_PHA |
PORT37_LPSPI0_PCS0 |
PORT40_SAI1_BCLK |
PORT41_SAI1_D0 |
PORT42_SAI1_MCLK |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT45_CAN2_TX |
PORT45_CAN2_TX |
PORT45_CAN2_TX */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT49_FTM5_FLT1 |
PORT49_FTM5_FLT1 |
PORT50_LPSPI1_PCS1 |
PORT50_LPSPI1_PCS1 |
PORT55_MII_COL */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(7)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_1 |
PORT65_MII_RMII_RXD_1 |
PORT66_LPUART0_RX |
PORT67_LPUART0_TX |
PORT69_LPI2C1_HREQ |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT70_FTM3_CH2 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT71_FTM3_CH3 |
PORT72_FTM5_CH1 |
PORT72_FTM5_CH1 |
PORT73_FTM5_CH0 |
PORT73_FTM5_CH0 |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT76_LPUART2_CTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT77_LPUART2_RTS |
PORT78_MII_COL |
PORT79_MII_CRS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_LPI2C1_SDAS |
PORT81_LPI2C1_SCLS |
PORT85_FTM7_FLT0 |
PORT94_LPI2C1_SDAS |
PORT95_LPI2C1_SDA */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT96_FTM2_CH0 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT97_FTM2_CH1 |
PORT98_FXIO_D4 |
PORT99_FXIO_D5 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT101_FTM2_FLT1 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT102_FTM2_FLT2 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT103_FTM2_FLT3 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT104_FTM2_FLT2 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT105_FTM2_FLT3 |
PORT106_ETM_TRACE_D3 |
PORT107_ETM_TRACE_D2 |
PORT108_ETM_TRACE_D1 |
PORT111_LPSPI0_SCK */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_LPSPI0_SIN |
PORT113_FTM5_FLT1 |
PORT113_FTM5_FLT1 |
PORT114_LPI2C1_SCLS |
PORT115_LPI2C1_SCL */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3)
          ),
/* Pads 128 ... 143 : PORT128_LPI2C1_SDA |
PORT129_LPI2C1_SCL |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT130_FTM3_CH6 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT131_FTM2_FLT0 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT132_FTM2_CH2 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT133_FTM2_CH3 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT134_FTM3_CH7 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT138_FTM2_CH4 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT139_FTM2_CH5 |
PORT140_FTM5_FLT0 |
PORT140_FTM5_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT141_FTM2_FLT0 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT142_FTM2_FLT1 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 |
PORT143_FTM2_CH6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 |
PORT144_FTM2_CH7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT1_FTM1_QD_PHA |
PORT2_FXIO_D4 |
PORT3_FXIO_D5 |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT11_CMP0_RRT |
PORT15_FTM7_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_FTM5_FLT0 |
PORT17_FTM5_FLT0 |
PORT18_FTM6_CH0 |
PORT27_CAN0_TX |
PORT27_CAN0_TX |
PORT28_CAN0_RX |
PORT28_CAN0_RX |
PORT29_LPSPI1_SIN |
PORT29_LPSPI1_SIN */
  (uint16)( SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  32 ...  47 : PORT32_CAN0_RX |
PORT33_CAN0_TX |
PORT36_MII_RMII_MDIO |
PORT37_CLKOUT |
PORT44_FTM6_FLT1 |
PORT45_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT54_LPUART1_TX |
PORT54_LPUART1_TX |
PORT57_LPSPI2_PCS0 |
PORT57_LPSPI2_PCS0 |
PORT59_LPSPI2_SOUT |
PORT59_LPSPI2_SOUT |
PORT60_LPSPI2_SIN |
PORT60_LPSPI2_SIN |
PORT61_LPSPI2_SCK |
PORT61_LPSPI2_SCK */
  (uint16)( SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_MII_RMII_RXD_0 |
PORT65_MII_RMII_RXD_0 |
PORT66_MII_RMII_TXD_0 |
PORT67_MII_TX_ER |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN |
PORT68_EWM_IN */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4)
          ),
/* Pads  80 ...  95 : PORT80_MII_RMII_RX_ER |
PORT81_MII_RMII_RX_DV |
PORT83_LPSPI2_PCS1 |
PORT83_LPSPI2_PCS1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3)
          ),
/* Pads  96 ... 111 : PORT96_ETM_TRACE_D0 |
PORT97_SAI0_MCLK |
PORT98_FXIO_D6 |
PORT99_FXIO_D7 |
PORT101_MII_TXD3 |
PORT102_MII_TXD2 |
PORT103_MII_RMII_TXD_1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT104_FXIO_D1 |
PORT105_MII_RXD2 |
PORT106_MII_RX_CLK |
PORT107_MII_RMII_TX_CLK |
PORT108_MII_RMII_TX_EN |
PORT109_ENET_TMR1 |
PORT110_ENET_TMR0 |
PORT111_ENET_TMR2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_CMP0_RRT |
PORT127_FTM6_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_LPSPI1_SOUT |
PORT129_LPSPI1_PCS0 |
PORT132_CAN0_RX |
PORT133_CAN0_TX |
PORT136_MII_RMII_MDC |
PORT137_ENET_TMR3 |
PORT143_FTM4_FLT1 |
PORT143_FTM4_FLT1 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FTM4_FLT0 |
PORT144_FTM4_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPUART0_CTS |
PORT1_LPUART0_RTS |
PORT2_LPUART0_RX |
PORT3_LPUART0_TX |
PORT6_LPUART1_CTS |
PORT7_LPUART1_RTS |
PORT8_FTM4_FLT1 |
PORT8_FTM4_FLT1 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT11_SAI0_SYNC |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT32_FTM4_CH6 |
PORT32_FTM4_CH6 |
PORT33_FTM4_CH5 |
PORT33_FTM4_CH5 |
PORT34_TRGMUX_IN3 |
PORT35_TRGMUX_IN2 |
PORT36_TRGMUX_IN1 |
PORT37_TRGMUX_IN0 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_FTM1_CH6 |
PORT65_FTM1_CH7 |
PORT66_ETM_TRACE_CLKOUT |
PORT67_QSPI_A_CS |
PORT68_FTM1_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT69_FTM2_QD_PHB |
PORT70_FTM1_QD_PHB |
PORT71_FTM1_QD_PHA |
PORT72_LPUART0_CTS |
PORT73_LPUART0_RTS |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT74_TRGMUX_IN11 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT75_TRGMUX_IN10 |
PORT78_TRGMUX_IN9 |
PORT79_TRGMUX_IN8 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          ),
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT96_FXIO_D0 |
PORT97_FXIO_D1 |
PORT98_TRGMUX_IN5 |
PORT99_TRGMUX_IN4 |
PORT101_TRGMUX_IN7 |
PORT103_ETM_TRACE_D0 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT104_FTM1_CH4 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT105_FTM1_CH5 |
PORT106_CLKOUT |
PORT106_CLKOUT |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT107_LPUART2_CTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS |
PORT108_LPUART2_RTS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12)
          ),
/* Pads 112 ... 127 : PORT112_ETM_TRACE_CLKOUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 128 ... 143 : PORT128_FTM1_FLT2 |
PORT129_FTM1_FLT1 |
PORT130_LPUART1_CTS |
PORT131_TRGMUX_IN6 |
PORT132_FXIO_D6 |
PORT133_FXIO_D7 |
PORT134_LPUART1_RTS |
PORT138_FXIO_D4 |
PORT139_FXIO_D5 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 |
PORT143_FXIO_D2 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 |
PORT144_FXIO_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_TRGMUX_OUT3 |
PORT1_TRGMUX_OUT0 |
PORT4_JTAG_TMS_SWD_DIO |
PORT5_RESET_b |
PORT9_FTM4_FLT0 |
PORT9_FTM4_FLT0 |
PORT10_JTAG_TDO |
PORT12_SAI0_BCLK |
PORT13_SAI0_D0 |
PORT14_SAI0_D3 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT36_QSPI_B_IO0 |
PORT37_MII_RMII_MDC */
  (uint16)( SHL_PAD_U16(4) |
            SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_QSPI_B_RWDS |
PORT65_QSPI_B_SCK |
PORT66_QSPI_A_IO3 |
PORT67_QSPI_B_IO3 |
PORT68_JTAG_TCLK_SWD_CLK |
PORT69_JTAG_TDI |
PORT79_QSPI_B_CS */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_QSPI_B_IO7 |
PORT81_QSPI_B_IO6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1)
          ),
/* Pads  96 ... 111 : PORT96_TRGMUX_OUT1 |
PORT97_TRGMUX_OUT2 |
PORT99_NMI_b |
PORT101_QSPI_B_IO2 |
PORT102_QSPI_B_IO1 |
PORT103_QSPI_A_IO1 |
PORT104_QSPI_B_IO5 |
PORT105_QSPI_B_IO4 |
PORT106_QSPI_A_SCK |
PORT107_QSPI_A_IO0 |
PORT108_QSPI_A_IO2 |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT109_RTC_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT |
PORT110_CLKOUT */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT128_SAI0_D2 |
PORT129_SAI0_D1 |
PORT130_SAI1_SYNC |
PORT131_CMP0_OUT |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT132_EWM_OUT_b |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT133_EWM_IN |
PORT138_TRGMUX_OUT4 |
PORT139_TRGMUX_OUT5 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 |
PORT143_TRGMUX_OUT6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 |
PORT144_TRGMUX_OUT7 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}

[!ENDVAR!]




[!VAR "CHECK_"!]

/*  Mode PORT_ALT0_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_ADC0_SE0_CMP0_IN0 |
PORT1_ADC0_SE1_CMP0_IN1 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT2_ADC1_SE0 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT3_ADC1_SE1 |
PORT6_ADC0_SE2 |
PORT7_ADC0_SE3 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 |
PORT15_ADC1_SE12 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT14_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT15_GPIO |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 |
PORT16_ADC1_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT0_FTM2_CH1 |
PORT1_FTM1_CH1 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT2_FTM3_CH0 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT3_FTM3_CH1 |
PORT6_FTM0_FLT1 |
PORT7_FTM0_FLT2 |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT8_LPUART2_RX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT9_LPUART2_TX |
PORT10_FTM1_CH4 |
PORT11_FTM1_CH5 |
PORT12_FTM1_CH6 |
PORT13_FTM1_CH7 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT14_FTM0_FLT0 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT15_FTM1_CH2 |
PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT16_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT20_GPIO |
PORT21_GPIO |
PORT22_GPIO |
PORT23_GPIO |
PORT24_GPIO |
PORT25_GPIO |
PORT25_GPIO |
PORT26_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT30_GPIO |
PORT31_GPIO |
PORT31_GPIO |
PORT32_ADC0_SE4_ADC1_SE14 |
PORT33_ADC0_SE5_ADC1_SE15 |
PORT34_ADC0_SE6 |
PORT35_ADC0_SE7 |
PORT38_XTAL |
PORT39_EXTAL |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT44_ADC1_SE7 |
PORT45_ADC1_SE8_ADC0_SE8 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT46_ADC1_SE9_ADC0_SE9 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 |
PORT47_ADC1_SE14 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPI2C0_SCLS |
PORT1_LPI2C0_SDAS |
PORT2_LPI2C0_SDA |
PORT3_LPI2C0_SCL |
PORT5_TCLK1 |
PORT6_LPSPI1_PCS1 |
PORT7_FTM5_CH3 |
PORT7_FTM5_CH3 |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT8_LPSPI2_SOUT |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT9_LPSPI2_PCS0 |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT12_CAN1_RX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT13_CAN1_TX |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT14_FTM3_FLT1 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT15_LPSPI0_PCS3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT16_FTM1_CH3 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT17_FTM0_CH6 |
PORT18_FTM4_CH0 |
PORT19_FTM4_CH1 |
PORT20_FTM4_CH2 |
PORT21_FTM4_CH3 |
PORT22_FTM4_CH4 |
PORT23_FTM4_CH6 |
PORT24_FTM4_CH7 |
PORT25_FTM5_CH0 |
PORT25_FTM5_CH0 |
PORT26_FTM5_CH1 |
PORT26_FTM5_CH1 |
PORT27_FTM5_CH2 |
PORT27_FTM5_CH2 |
PORT28_FTM5_CH3 |
PORT28_FTM5_CH3 |
PORT29_FTM5_CH4 |
PORT29_FTM5_CH4 |
PORT30_FTM5_CH5 |
PORT30_FTM5_CH5 |
PORT31_FTM5_CH6 |
PORT31_FTM5_CH6 |
PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT46_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT47_GPIO |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT48_ADC1_SE15 |
PORT50_ADC0_SE16 |
PORT50_ADC0_SE16 |
PORT52_ADC0_SE17 |
PORT52_ADC0_SE17 |
PORT53_ADC0_SE18 |
PORT53_ADC0_SE18 |
PORT54_ADC0_SE19 |
PORT54_ADC0_SE19 |
PORT55_ADC0_SE20 |
PORT55_ADC0_SE20 |
PORT57_ADC0_SE21 |
PORT57_ADC0_SE21 |
PORT59_ADC0_SE22 |
PORT59_ADC0_SE22 |
PORT60_ADC0_SE23 |
PORT60_ADC0_SE23 |
PORT61_ADC0_SE24 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FXIO_D2 |
PORT1_FXIO_D3 |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT2_EWM_OUT_b |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT3_EWM_IN |
PORT4_CMP0_OUT |
PORT6_FTM5_CH5 |
PORT6_FTM5_CH5 |
PORT7_RTC_CLKIN |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT8_FXIO_D6 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT9_FXIO_D7 |
PORT10_FXIO_D0 |
PORT11_FXIO_D1 |
PORT12_LPI2C1_SDAS |
PORT13_LPI2C1_SCLS |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT14_EWM_IN |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 |
PORT15_LPSPI2_PCS3 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT16_LPSPI1_PCS2 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT17_FTM3_FLT0 |
PORT18_LPUART1_TX |
PORT19_LPUART1_RX |
PORT21_FXIO_D0 |
PORT22_FXIO_D1 |
PORT23_FXIO_D2 |
PORT24_FXIO_D3 |
PORT26_LPSPI1_PCS0 |
PORT26_LPSPI1_PCS0 |
PORT27_LPSPI1_SOUT |
PORT27_LPSPI1_SOUT |
PORT28_LPSPI1_SCK |
PORT28_LPSPI1_SCK |
PORT30_LPUART2_RX |
PORT30_LPUART2_RX |
PORT32_LPUART0_RX |
PORT33_LPUART0_TX |
PORT34_FTM1_CH0 |
PORT35_FTM1_CH1 |
PORT36_FTM0_CH4 |
PORT37_FTM0_CH5 |
PORT38_LPI2C0_SDA |
PORT39_LPI2C0_SCL |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT40_FTM3_CH0 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT41_FTM3_CH1 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT42_FTM3_CH2 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT43_FTM3_CH3 |
PORT44_FTM0_CH0 |
PORT45_FTM0_CH1 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT46_FTM0_CH2 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT47_FTM0_CH3 |
PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT48_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT49_GPIO |
PORT50_GPIO |
PORT50_GPIO |
PORT51_GPIO |
PORT52_GPIO |
PORT52_GPIO |
PORT53_GPIO |
PORT53_GPIO |
PORT54_GPIO |
PORT54_GPIO |
PORT55_GPIO |
PORT55_GPIO |
PORT56_GPIO |
PORT57_GPIO |
PORT57_GPIO |
PORT58_GPIO |
PORT59_GPIO |
PORT59_GPIO |
PORT60_GPIO |
PORT60_GPIO |
PORT61_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO |
PORT64_ADC0_SE8 |
PORT65_ADC0_SE9 |
PORT66_ADC0_SE10_CMP0_IN5 |
PORT67_ADC0_SE11_CMP0_IN4 |
PORT68_CMP0_IN2 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT70_ADC1_SE4 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT71_ADC1_SE5 |
PORT78_ADC0_SE12 |
PORT79_ADC0_SE13 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT0_FTM2_QD_PHA |
PORT1_FTM1_QD_PHA |
PORT2_FXIO_D4 |
PORT3_FXIO_D5 |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT4_EWM_OUT_b |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT8_FTM3_FLT3 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT9_FTM3_FLT2 |
PORT11_CMP0_RRT |
PORT15_FTM7_FLT0 |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT17_EWM_OUT_b |
PORT18_LPSPI1_SOUT |
PORT19_LPSPI1_SCK |
PORT20_LPSPI1_SIN |
PORT21_LPSPI1_PCS0 |
PORT22_LPSPI1_PCS1 |
PORT26_LPSPI0_PCS0 |
PORT26_LPSPI0_PCS0 |
PORT27_LPUART0_TX |
PORT27_LPUART0_TX |
PORT28_LPUART0_RX |
PORT28_LPUART0_RX |
PORT29_LPUART2_TX |
PORT29_LPUART2_TX |
PORT30_LPSPI0_SOUT |
PORT30_LPSPI0_SOUT |
PORT31_LPSPI0_PCS1 |
PORT31_LPSPI0_PCS1 |
PORT32_LPSPI0_PCS0 |
PORT33_LPSPI0_SOUT |
PORT34_LPSPI0_SCK |
PORT35_LPSPI0_SIN |
PORT36_LPSPI0_SOUT |
PORT37_LPSPI0_PCS1 |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT41_LPI2C0_SCLS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT42_LPI2C0_SDAS |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT43_LPI2C0_HREQ |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT44_FTM3_FLT2 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT45_FTM3_FLT1 |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT46_LPSPI1_SCK |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT47_LPSPI1_SIN |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT48_FTM0_CH4 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT49_FTM0_CH5 |
PORT50_FTM5_CH7 |
PORT50_FTM5_CH7 |
PORT51_FTM5_CH7 |
PORT52_FTM6_CH0 |
PORT53_FTM6_CH1 |
PORT54_FTM6_CH2 |
PORT55_FTM6_CH3 |
PORT56_FTM6_CH4 |
PORT57_FTM6_CH5 |
PORT58_FTM6_CH6 |
PORT59_FTM6_CH7 |
PORT60_FTM7_CH0 |
PORT61_FTM7_CH1 |
PORT62_FTM7_CH2 |
PORT63_FTM7_CH3 |
PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO |
PORT80_ADC0_SE14 |
PORT81_ADC0_SE15 |
PORT83_ADC0_SE25 |
PORT87_ADC0_SE26 |
PORT91_ADC0_SE27 |
PORT92_ADC0_SE28 |
PORT93_ADC0_SE29 |
PORT94_ADC0_SE30 |
PORT95_ADC0_SE31 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_LPUART0_CTS |
PORT1_LPUART0_RTS |
PORT2_LPUART0_RX |
PORT3_LPUART0_TX |
PORT6_LPUART1_CTS |
PORT7_LPUART1_RTS |
PORT8_FTM4_FLT1 |
PORT8_FTM4_FLT1 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT9_FTM1_FLT3 |
PORT11_SAI0_SYNC |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT12_FTM2_QD_PHB |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT13_FTM2_QD_PHA |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT14_FTM1_FLT0 |
PORT17_FTM5_FLT0 |
PORT17_FTM5_FLT0 |
PORT18_FTM6_CH0 |
PORT27_CAN0_TX |
PORT27_CAN0_TX |
PORT28_CAN0_RX |
PORT28_CAN0_RX |
PORT29_LPSPI1_SIN |
PORT29_LPSPI1_SIN |
PORT32_LPTMR0_ALT3 |
PORT33_TCLK0 |
PORT34_FTM1_QD_PHB |
PORT35_FTM1_QD_PHA |
PORT37_LPSPI0_PCS0 |
PORT40_SAI1_BCLK |
PORT41_SAI1_D0 |
PORT42_SAI1_MCLK |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT44_CAN2_RX |
PORT45_CAN2_TX |
PORT45_CAN2_TX |
PORT45_CAN2_TX |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT48_LPSPI1_SOUT |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT49_LPSPI1_PCS3 |
PORT54_MII_CRS |
PORT55_LPUART1_RX |
PORT55_LPUART1_RX |
PORT64_FTM0_CH0 |
PORT65_FTM0_CH1 |
PORT66_FTM0_CH2 |
PORT67_FTM0_CH3 |
PORT68_FTM1_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT69_FTM2_CH0 |
PORT70_LPUART1_RX |
PORT71_LPUART1_TX |
PORT72_LPUART1_RX |
PORT73_LPUART1_TX |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT74_FTM3_CH4 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT75_FTM3_CH5 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT76_FTM3_CH6 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT77_FTM3_CH7 |
PORT78_FTM1_CH2 |
PORT79_FTM1_CH3 |
PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT94_GPIO |
PORT95_GPIO |
PORT95_GPIO |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT98_ADC1_SE2 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT99_ADC1_SE3 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT100_ADC1_SE6 |
PORT102_CMP0_IN7 |
PORT103_CMP0_IN6 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_TRGMUX_OUT3 |
PORT1_TRGMUX_OUT0 |
PORT4_JTAG_TMS_SWD_DIO |
PORT5_RESET_b |
PORT9_FTM4_FLT0 |
PORT9_FTM4_FLT0 |
PORT10_JTAG_TDO |
PORT12_SAI0_BCLK |
PORT13_SAI0_D0 |
PORT14_SAI0_D3 |
PORT32_CAN0_RX |
PORT33_CAN0_TX |
PORT36_MII_RMII_MDIO |
PORT37_CLKOUT |
PORT44_FTM6_FLT1 |
PORT45_FTM6_FLT0 |
PORT49_FTM5_FLT1 |
PORT49_FTM5_FLT1 |
PORT50_LPSPI1_PCS1 |
PORT50_LPSPI1_PCS1 |
PORT55_MII_COL |
PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT64_LPSPI2_SIN |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT65_LPSPI2_SOUT |
PORT66_CAN0_RX |
PORT67_CAN0_TX |
PORT68_RTC_CLKOUT |
PORT69_RTC_CLKOUT |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT70_CAN1_RX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT71_CAN1_TX |
PORT72_FTM1_FLT0 |
PORT73_FTM1_FLT1 |
PORT75_FTM4_CH2 |
PORT75_FTM4_CH2 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT76_FTM2_CH6 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT77_FTM2_CH7 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT78_LPSPI2_PCS0 |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK |
PORT79_LPSPI2_SCK |
PORT80_FTM1_FLT2 |
PORT81_FTM1_FLT3 |
PORT82_FTM7_CH4 |
PORT83_FTM7_CH5 |
PORT84_FTM7_CH6 |
PORT85_FTM7_CH7 |
PORT86_FTM7_FLT1 |
PORT87_LPSPI0_SCK |
PORT87_LPSPI0_SCK |
PORT88_FTM4_CH0 |
PORT89_FTM4_CH1 |
PORT90_FTM4_CH3 |
PORT91_FTM4_CH4 |
PORT91_FTM4_CH4 |
PORT92_FTM4_CH7 |
PORT92_FTM4_CH7 |
PORT93_FTM5_CH2 |
PORT93_FTM5_CH2 |
PORT94_FTM5_CH4 |
PORT94_FTM5_CH4 |
PORT95_FTM5_CH6 |
PORT95_FTM5_CH6 |
PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT110_GPIO |
PORT111_GPIO |
PORT114_ADC1_SE16 |
PORT114_ADC1_SE16 |
PORT115_ADC1_SE17 |
PORT115_ADC1_SE17 |
PORT118_ADC1_SE18 |
PORT118_ADC1_SE18 |
PORT119_ADC1_SE19 |
PORT119_ADC1_SE19 |
PORT120_ADC1_SE20 |
PORT120_ADC1_SE20 |
PORT123_ADC1_SE21 |
PORT123_ADC1_SE21 |
PORT124_ADC1_SE22 |
PORT124_ADC1_SE22 |
PORT125_ADC1_SE23 |
PORT125_ADC1_SE23 |
PORT126_ADC1_SE24 */
  (uint16)( SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(0) |
            SHL_PAD_U16(1) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(4) |
            SHL_PAD_U16(5) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(9) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(10) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(14) |
            SHL_PAD_U16(15) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(2) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(3) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(6) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(7) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(8) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(11) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(12) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(13) |
            SHL_PAD_U16(14)
          )
}

[!ENDVAR!]



[!ENDIF!][!//avoid multiple inclusion
